H.H. WILLS PHYSICS LABORATORY, UNIVERSITY OF BRISTOL, BRISTOL, BS8 1TL, UK

Transcription

1 Achieving the Best Thermal Performance for -on- J. Pomeroy a *, M. Bernardoni a, A. Sarua a, A. Manoi a, D.C. Dumka b, D.M. Fanning b, M. Kuball a A H.H. WILLS PHYSICS LABORATORY, UNIVERSITY OF BRISTOL, BRISTOL, BS8 1TL, UK B TRIQUINT SEMICONDUCTOR, INC., 500 W. RENNER ROAD, RICHARDSON, TX, 75080, USA *James.Pomeroy@bristol.ac.uk 1

2 Outline Aim: Optimize thermal resistance in -on- through measurement and modelling Review state-of-the-art -on- transistor versus -on-sic Novel thermal resistance measurement: Substrate thermal conductivity Interfacial thermal resistance Validated transistor model for identifying thermal bottle necks in -on- Summary 2

3 Motivation High RF output power density in -based HEMTs requires improved thermal management Multifinger HEMT thermal image D G S heat 1µm Thermal resistances near the HEMT channel: epilayer + /substrate interface + Substrate Substrate - interface Thermal conductivity can be improved up to 5, replacing SiC->diamond 3

4 Temperature channel tremperature rise [ o C] Review: -on- State-of-the-art Advantage over -on- SiC already demonstrated: 10.8 Cmm/W (D.C. Dumka, F.4 CSICS 2013) How can we improve -on- even further? Peak channel temperature derived from Raman measurement µm, 2 Finger HEMT /mm Power density [W/mm] 4

5 Temperature rise [ o C] Historical Development Using experimental feedback to aid design 200 2xµm HEMT comparison κ 160 W/mK κ 16 W/mK Al T.L. Al interlayer 150 /Si /Tr. layer/ / Si transistors originate from on-si growth -ondiamond Including transition layer Current design, T.L. removed 50 Raman measured temperature Power density [W/mm] Lets examine thermal resistance in more detail 5

6 Thermal Resistance Components 160 W/mK TBR eff?: Effective thermal resistance of interface region, including dielectric + diamond nucleation layer (< nm) κ diamond?: Thermal conductivity depends on grain size. Bulk thermal conductivity measurements may be misleading for device modelling 1µm 25nm dielectric 95 µm polycrystalline diamond Increasing thermal conductivity along growth direction -> Aim: Separate these thermal resistance contributions 6

7 Temperature rise [ o C] Raman Thermography Depth Mapping Ungated transistor as a uniform heat source Temperature gradient->thermal parameters substrate TBR eff - Substrate 150 TBR eff Substrate thermal conductivity 50 Confocal depth mapping through transparent uniform materials Log. Depth [ m] Raman temperature mapping through polycrystalline diamond is challenging: Light absorption and stress variation 7

8 Temperaure [ o C] centre mesa edge Surface Temperature Profile For highest accuracy, we measure the temperature in the uniform layer, rather than the diamond F.E. model of ungated HEMT ¼ cross section Polycrystalline map mesa Position [microns] interface Fit finite element model by adjusting two parameters: thermal conductivity + /diamond interface TBR eff 8

9 temperature [Deg. C] Thermal Resistance Measurement Opaque diamond Effective diamond substrate thermal conductivity = 710±40 W/mK 70% increase over SiC /diamond TBR eff = 2.7± m 2 K/W W map Measurement Simulation mesa Comparable to typical on-sic TBR Will result in lower transistor thermal resistance than -on-sic Position [microns] 9

10 Interface Temperature [Deg. C] Validating Thermal Model 25nm dielectric Measurement Probed region 1µm 0.5µm Model input parameters are fixed Simulation measurement measurement 3.36W Opaque diamond enables measured diamond temperature to be compared to model Depth [ m] Self consistency between measurement and model 10

11 Interface Temperature [Deg. C] Effective Substrate Thermal Conductivity Simulation measurement measurement Lower Thermal conductivity gradient Higher 2-D-like heat diffusion Depth [ m] Effective thermal conductivity < bulk thermal conductivity Effective thermal conductivity is relevant for transistor modelling Region of highest sensitivity ~30µm 11

12 stress [GPa] Wafer 2: Higher Grade Raman temperature mapping though translucent diamond is difficult, due to stress variations Image taken though diamond substrate Depth [microns] surface temperature mapping approach can still be applied with high accuracy 12

13 temperature [Deg. C] Wafer 2: Thermal Measurement 1200 W/mK effective diamond thermal conductivity Thicker 50nm interlayer (w.r.t opaqe wafer), resulting in a 40% higher interface thermal resistance 160 Measurement Simulation W map mesa Position [microns] What is the relationship between interface thermal resistance, substrate thermal conductivity and transistor thermal resistance? 13

14 Temperature rise [ o C] Transistor Thermal Model Opaque diamond wafer, 2 µm HEMT, P diss = 15.3 W/mm Source interface Gate Drain on-sic 40% Measurement: Simulation: diamond R interface W/mK o Cm 2 /W x10-8 Parameters obtained earlier Raman probe 1 µm Model validation: Agreement with measured temperatures Depth [ m] 14

15 Temperature rise [ o C] Reducing Transistor Thermal Resistance Use validated transistor model to explore thermal resistance components -on-sic Current -on-diamond Increasing diamond thermal conductivity S G D diamond Measurement: Simulation: diamond R interface W/mK o Cm 2 /W x x OR decreasing interface thermal resistance Eliminating / interface resistance reduces transistor thermal resistance by a further 35% Depth [ m] 15

16 Summary A 40% reduction in channel thermal resistance has been demonstrated for current -on-diamond transistors versus -on-sic A further 35% reduction in transistor thermal resistance could be achieved by reducing the /diamond interface thermal resistance A methodology has been developed for characterising the thermal resistance components of -on-: Effective diamond thermal conductivity W/mK / interfacial thermal resistance 2.7± m 2 K/W for 25 nm interlayer Acknowledgement: This work is supported by the DARPA Near Junction Thermal Transport (NJTT) Program, monitored by Dr. Avi Bar Cohen, Dr. Joe Maurer and Dr. Jonathan Felbinger of DARPA. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of DARPA. 16