Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Transcription

1 Microelectronics Reliability 42 (2002) Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies C.F. Luk a,1, Y.C. Chan b, *, K.C. Hung b a SAE Magnetics (HK) Ltd., SAE Tower, Kwai Fung Crescent, Kwai Chung, NT, Hong Kong b Department of Electronic Engineering, City University of Hong Kong, 83 Tat Chee Avenue, Kowloon, Hong Kong Received 19 September 2001; received in revised form 5 November 2001 Abstract Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension. This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability. Ó 2002 Elsevier Science Ltd. All rights reserved. 1. Introduction Data storage industries have witnessed an annual compound growth rate in area density of magnetic recording of 60% since 1991 and 100% since Central to this phenomenal growth has been the continual breakthroughs in magnetic recording technology and periphery to it is a whole range of supporting technologies, of which the high density interconnect for integrating the magnetic recording MR head to the drive electronics is one of the most important breakthrough. Disk-drive designers have been moving the drive IC ever close to the read/write magnetic recording head in an effort to reduce the parasitic load of the flexible interconnect and improve channel performance by reducing * Corresponding author. Tel.: ; fax: addresses: cfluk@sae.com.hk (C.F. Luk), eeycchan@cityu.edu.hk (Y.C. Chan). 1 Tel.: ; fax: noise and signal degradation. Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and accordingly shorten the overall cycle time. The subsequent benefit of this reduces manufacturing cost by capital investment reduction in processing equipment and fast work-in-progress. Head gimbal assembly (HGA) is the core component in a magneto-resistive (MR) head where read/write exchange process takes place. A new HGA configuration with the integrated circuit suspension design was developed by component suppliers to make the chip on suspension (COS) concept become practical [1]. This new HGA configuration was developed from the conventional HGA with twist pair wires design (see Fig. 1) /02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S (01)

2 382 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Fig. 1. The HGA configuration trends. With the circuit integrated suspension design, it becomes possible to assemble the drive IC chip so that it can be close to the MR head slider on the suspension (see Fig. 2). Distance reduction between the drive IC chip and the MR head slider decreases the parasitic resistance, inductance, and capacitance. With the lowest parasitic impedance, in other words, a clean data transmission line, higher data transfer rates entering the 700 Mb/s to 1 Gb/s regime can be achieved. This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI. Au bumps, which are applied mechanically on the wafer or on the chip by thermosonic ball bonder can make fine pitch bumping. The process can be applicable to chips having peripheral bond pads of pitch size down to 80 lm. In the present study, the total GGI process is evaluated. The bumping of the incoming die, the flip chip assembly processes from the pick and place of the die, Au to Au interconnection bonding and the underfill process to fill up the die/substrate gap is investigated. Characterization of the critical GGI process parameters such as heating temperature, bonding pressure, ultrasonic power setting and duration time for optimal Fig. 2. HGA with COS. bonding condition is established. The reliability evaluation is concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. Performed tests are ball bond shear test, high temperature storage, and temperature cycling and humidity storage. X-ray inspection for Au bumps positional precision with respect to the Au bond pads is also studied. Underfill quality is revealed by SAM inspection for void, crack and delamination defects. 2. Gold to gold interconnection process A flip-chip bonder with an ultrasonic tool was used to perform the COS assembly evaluation. Prior to the Au to Au interconnection bonding, co-planarity of the die and the substrate must be carefully aligned to achieve good bonding. The bonding procedure begins with the substrate sitting on a heated stage. A vacuum holds the substrate in the work holder. The temperature of the substrate is heated from 120 to 200 C. The chip is held by the bonding tool with vacuum and is brought into the contact with the substrate. After the bonding force has reached a certain level, ultrasonic vibration is applied through the ultrasonic tool for a predetermined length of time to complete the process. In GGI thermosonic bonding technique, the principal features of ultrasonic and thermocompression bonding are combined to form a good joint. The steps in GGI process are shown in Fig. 3. Step 1: Bonding tool picks up the IC chip by vacuum suction and aligns the gold bumps with the substrate bond pads. The work stage is heated at 150 C. Step 2: The bonding tool lowers down and presses the IC chip against the bond pads of the substrate till there is no clearance between the interfaces of IC chip/ tool and IC chip/substrate bond pad. Step 3: Ultrasonic power deforms gold stud bump and touches to bonding pad tightly so pad metallurgy diffuses into gold bump. Step 4: After bonding completes, vacuum force is released from the bonding tools and the tool rises up.

3 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Fig. 3. US bonding procedure. Bonding parameters for good GGI bonding, include heating temperature, bonding pressure, ultrasonic power and time duration. 3. Experimentation In thermosonic method the bonding between gold bumps and substrate metallization is accomplished by applying a force and ultrasonic power to the back of the chip. In addition to force and power important parameter effecting bond quality are time and substrate temperature. Optimization and characterization of the COS process was performed by using simple ball shear test. The die shear strength is recorded as a function of the critical process variables. The process windows and dependencies are determined for specific process variables such as pressure, time, power and temperature. Once the process window was determined an optimal cycle was chosen to further characterize the system performance. bonding techniques where the wire is fractured after ball bond formation. The wire stud bumps can be coined to form uniform structure for bonding. The specification of the IC chip dimensions is shown below: chip size: 1:4ðLÞ1:1ðWÞ0:125ðHÞ mm 3 ; bump material: gold; count of bumps: 8 bumps; pad-to-pad distance: A ¼ 0:19 mm, B ¼ 0:26 mm (cf. Fig. 4); bump size: D ¼ 0:105 mm, H2 ¼ 25:4 lm, H1 ¼ 40 lm (cf. Fig. 5). 4. Description of chip on suspension assembly components 4.1. Integrated circuit chip The IC chip used in the COS evaluation is 803AC pre-amp. Wire stud bumps are formed using a ball Fig. 4. IC chip.

4 384 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Fig. 5. Au stud bump. Fig. 6. Cross-section of suspension pads. Fig. 7. The picture of the ball bond shear tester. Au-plated surface finish is required for the substrate to have a good bonding with the gold stud bumped IC by thermosonic bonding method Integrated circuit suspension The integrated circuit suspension is used in this experiment. Bonding pads surface finish is Ni Au plated. The material structure and thickness of different layers for the integrated suspension substrate are shown in Fig. 6. up condition for test die and tool positioning is shown in Fig. 8. Step 1: Load test sample onto the sample holder. Step 2: Rotate the tester work stage for proper alignment of the bonded chip and contact tool. Step 3: Adjust the micrometer for the X Y alignment so that the test tool and test die are in line. Step 4: Set the contact tool to proper height (7 lm) above the substrate. Step 5: Perform the shear test. Step 6: Read the shear strength from the load cell counter. Step 7: Examine and record the failure mode under the microscope. 5. Results and discussion 5.1. Ball shear test The equipment used to perform the ball bond shear test is an automatic shear tester with load cell range from 0 to 2500 g and reading tolerance 0.1 g. A motor drive moved the test sample work holder to perform the shear test at a fixed rate of 0.2 mm/s. Fig. 7 shows the picture of the ball bond shear tester. The test procedure is reference to MIL-STD-883E. The test steps are briefly described as below and the set Fig. 8. Test set up condition.

5 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Ball shear test failure modes for Au to Au interconnection Five typical failure modes of the ball shear test on the thermosonic Au to Au bonding are identified and are shown in Fig. 9. Failure mode A is the most desired shear test result which indicates bonding joints separate at the middle of the bump and there is bump residue on both the chip and substrate surface. Failure mode B shown marginal good test result with no silicon exposed. Failure mode C indicates potential risk of silicon crack of die. Failure mode D highlights the evidence of microcrack presented in the die surface as a result of the shear test. Failure mode E showed bonding process conditions not fully optimized. It is acceptable as long as shear strength meets target shear strength level. Fig. 9. GGI failure modes of the ball shear test.

6 386 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Optimization of the thermosonic Au Au bonding process Fig. 10 shows the relationship between the shear strength of COS samples and the ultrasonic time of the thermosonic bonding. It is commonly known that thermosonic Au Au bonding uses ultrasonic energy to soften the joint material and to promote the solid diffusion between the Au bump and the Au pad [2]. 0.1 s ultrasonic time will not be enough for softening joint material. Fig. 11 shows the optical micrograph of the crosssection of the COS sample using 0.1 s of ultrasonic time. It can be seen that the Au bump is not deformed properly and only the central part of the Au bump is directly bonded to the Au pad of the suspension and it will reduce the effective bonding area of the Au bump to the Au pad and cause the low shear strength of the COS sample. If the ultrasonic time is enough, the Au bump can be deformed so that good Au-Au bonding will be achieved (see Fig. 12). Fig. 13 shows the plot of the shear strength of COS samples against the bonding pressure. In order to interpret the results in Fig. 13, we also show the optical micrographs of the cross-section of COS samples in Fig. 14. As the bonding pressure increases, the Au bump is deformed more and larger effective contact area at the bonding interface between Au bump and Au pad is obtained. It can also be seen from Table 1 which shows the standoff height of the COS samples, the bonding pressure increment leads to reduction of standoff height from 33 to 18 lm. However, too high bonding pressure may result in damage to the device by the bonding tool [2]. Fig. 14 shows optical micrograph of cross-section of COS sample using different bonding pressure. Fig. 15 shows the relationship between the shear strength of COS samples and the ultrasonic power of the thermosonic bonding. Low power of ultrasonic energy is not enough for softening and bonding Au bump to Au Fig. 11. Optical micrograph of cross-section of COS sample using 0.1 s of ultrasonic time. Fig. 12. Optical micrograph of cross-section of COS sample using 0.5 s of ultrasonic time. Fig. 13. The plot of shear strength vs bonding pressure. Fig. 10. The plot of shear strength vs ultrasonic time. pad. As the ultrasonic power increases, the bonding strength increases. However, when the ultrasonic power

7 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Fig. 15. The plot of shear strength vs ultrasonic power. Fig. 14. Optical micrograph of cross-section of COS sample using different bonding pressure. increases to 26 mw, the shear strength is unexpectedly reduced. From our study and analysis, the larger the ultrasonic power, the larger the amplitude of the horntip vibration of the thermosonic bonder [3]. When the amplitude is too large, the fresh bond formed in a cycle may be broken in any cycle. As a result, this large amplitude movement may affect the efficiency of the bonding at the interface between Au bump and Au pad. Fig. 16 is the SEM picture of the sheared surface of the COS sample using ultrasonic power of 26 mw, which shows the evidence of the above postulation. It can be seen that some positions are not bonded well (see arrows). Therefore, too large ultrasonic amplitude will cause bad thermosonic bonding of the COS samples even though the effective bonding area of Au bump to Au pad is large enough. Fig. 17 shows the plot of the shear strength against the temperature provided to the substrate during thermosonic bonding. In fact, a higher substrate temperature leads to a better plastic deformation of the Au bump [4]. It can get a better bonding at a constant bonding force since a larger effective bonding area of Table 1 Bonding parameters vs standoff height Bonding parameters Standoff height (lm) Ultrasonic time (s) Bonding pressure (kg) Ultrasonic power (mw) Substrate temperature ( C) Fig. 16. SEM picture of the sheared surface of the COS sample using ultrasonic power of 26 mw.

8 388 C.F. Luk et al. / Microelectronics Reliability 42 (2002) Fig. 18. Bias current change under high temperature and high humidity storage (85 C and 85% RH). Fig. 17. The plot of shear strength vs substrate temperature. Au bump to Au pad is achieved. However, too high the substrate heating temperature will render warpage and degradation of substrate material and hence reduces the shear strength. From the detail evaluation of the above experiments, we can obtain a quite optimal setting of the thermosonic Au Au bonding of COS samples, which shows as follows: ultrasonic time ¼ 0:2 s; bonding pressure ¼ 0:45 kg; ultrasonic power ¼ 20 mw; substrate temperature ¼ 160 C. Fig. 19. Bias current change under thermal shock condition ( 40 to 125 C) Co-planarity and alignment Co-planarity is important to achieve good Au to Au thermosonic flip chip bonding. Parallelism and coplanarity adjustment of the ultrasonic tool with respect to the stainless suspension substrate must be achieved to obtain good Au to Au diffusion bonding. In our bonding parameter optimization process, both the co-planarity and alignment are controlled within 7 lm range Reliability of the optimal setting of the thermosonic Au Au bonding After the optimization of the bonding process, the chip and substrates were assembled with the selected process parameters. Underfill was dispensed after the bonding cycle and was cured for 2 h at 150 C. C-SAM inspection revealed the assembled parts are free from defects of crack, voids and delamination. Some standard reliability tests for the optimal setting have been performed. The reliability tests include high temperature and high humidity storage (85 C and 85% RH) for 1000 h, high temperature storage (125 C) for 1000 h, low temperature storage ( 40 C) for 1000 h, and thermal shock ( 40 to 125 C) for 1000 cycles. Figs are the plot of measured current of the COS samples against Fig. 20. Bias current change under low temperature storage ( 40 C). Fig. 21. Bias current change under high temperature storage (125 C).

9 C.F. Luk et al. / Microelectronics Reliability 42 (2002) the reliability testing time. These figures show that the standard reliability testing demonstrate a good reliability of the GGI COS samples. improve the limits of the technology with regard to reliability. 6. Conclusions COS design option will bring exciting new products to market and help to keep the hard disk drive industry on its current projected growth rate well into the decade. GGI flip chip bonding process has been successfully developed. Critical parameters affecting bond quality like ultrasonic force, power, time and substrate temperature are identified and their relationship to bond quality is expressed as a function of die shear strength. Reliability evaluations performed to the sample COS assemblies have shown good reliability of the GGI COS samples. Five typical ball shear test failure modes of COS assemblies by GGI bonding are identified. The failure mode (mode A) where bonding joint breaks between UBM and bump without silicon exposed is most desired. Since GGI flip chip bonding for COS application is still relatively new and has not been achieved for volume production, work is still being done to establish and Acknowledgements The authors would like to acknowledge the financial support provided by the Innovation and Technology Fund (project no ) of the Innovation and Technology Commission. References [1] Mclnerney B, Sheperek M. Chip-on-suspension electronics close preamp head gap. Data Storage 2000;7(12):34 8. [2] Lawyer PH, Choudhury D, Wetzel MD, Rensch DB. In: Electronics Manufacturing Technology Symposium, 23rd IEEE/CPMT, p [3] Kang S-Y, Ju T-H, Lee YC. In: Proceedings of the 43rd Electronic Components and Technology Conference, p [4] Weiss S, Zakel E, Reichl H. In: Proceedings of the 44th Electronic Components and Technology Conference, p