Fabrication of a Uniform Low Temperature Poly-Si TFT Array by Optimized Field Aided Lateral Crystallization

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1 Fabrication of a Uniform Low Temperature Poly-Si TFT Array by Optimized Field Aided Lateral Crystallization Jae Hoon Jung, Kwang Jin Lee, Duck Kyun Choi, Ji Hoon Shin, Jung Sun You and Young Bae Kim J. Electrochem. Soc. 2010, Volume 157, Issue 1, Pages H1-H5. doi: / alerting service Receive free alerts when new articles cite this article - sign up in the box at the top right corner of the article or click here To subscribe to Journal of The Electrochemical Society go to: ECS - The Electrochemical Society

2 Journal of The Electrochemical Society, H1-H /2009/157 1 /H1/5/$28.00 The Electrochemical Society Fabrication of a Uniform Low Temperature Poly-Si TFT Array by Optimized Field Aided Lateral Crystallization Jae Hoon Jung, a Kwang Jin Lee, a Duck Kyun Choi, a,z Ji Hoon Shin, b Jung Sun You, b and Young Bae Kim c a Department of Material Science and Engineering and b Department of Information Display Engineering, and c Information Display Research Institute, Hanyang University, Seoul , Korea H1 In this study, a 2 in. Ni field aided lateral crystallization FALC poly-si thin-film transistor TFT array was fabricated at the maximum process temperature of 500 C using an optimized current density distribution design. We investigated the correlation between crystallization and transistor characteristics in terms of transistor position in the array. Because an identical current density in the channel region of each pixel transistor was favorable to achieve uniform crystallization, an optimal common electrode design was chosen via Mathcad simulation. After the crystallization process, it was confirmed that the crystallinity variation in the transistor channels agreed well with the predicted simulation results. Furthermore, the positional variation in important transistor parameters in the array showed a good match with that of crystallization. The mean threshold voltage was 5.9 V V th = 0.2 V while the mean mobility was 92.5 cm 2 V 1 s 1 with a variation of 9.8%. These values suggested that the uniform Ni-FALC poly-si TFT arrays fabricated by the optimal design of the electrode were applicable to the active matrix organic light emitting display backplane The Electrochemical Society. DOI: / All rights reserved. Manuscript submitted February 24, 2009; revised manuscript received September 8, Published November 2, Low temperature polysilicon LTPS thin-film transistors TFTs are crucial elements of high resolution and reliable displays such as active matrix organic light emitting displays AMOLEDs. 1,2 For transistors to be used in an AMOLED backplane, they should have a high degree of uniformity DOU to satisfy the strict device parameters and specifications of driving TFTs including a threshold voltage V th of 0.3 V and a field-effect mobility FE of less than 10%. 3 Many LTPS methods to produce high quality poly-si 4-6 arrays, especially for applications in high resolution displays, have been suggested and explored for more than a decade. There are two major crystallization technologies: Laser technology and nonlaser technology. The former includes excimer laser annealing, 7,8 sequential laser solidification, 9 and selectively enlarging laser crystallization, 10 while the latter includes metal-induced crystallization, 11 metal-induced lateral crystallization, 12 and field aided lateral crystallization FALC. Among these methods, the most widely implemented is laser crystallization despite its drawbacks, which include a rough surface, 13 a narrow process window, difficulty in controlling the laser process, and beam length limitations. In contrast, FALC, which utilizes an ultrathin layer of metal catalyst and an electric field to induce a low temperature crystallization, does not have the limitations listed above and can be used to achieve uniform crystallization. Also, the FALC process has advantages over the other nonlaser technologies; the faster crystallization time, the lower crystallization temperature due to the electric field-assisted enhanced diffusivity of the crystallization mediator, the directional crystal growth that can enhance the mobility, and a lower leakage current as a result of driving out contaminants. 14,15 To apply the FALC process to the fabrication of pixel transistors on a large glass panel, a uniform current density in the individual channels of the pixel transistors in the array has to be achieved. The distribution of the current at the transistor node can be predicted by computer simulation. By changing the process parameters of FALC in simulations, the effect of these parameters on crystallization can be understood and predicted, and the simulation results obtained can be employed to design a mask for the electrode. The goal of this study was to investigate whether the FALC technique can be extended in a practical manner to a large panel. We fabricated a 2 in. poly-si TFT array, which is almost equivalent to a Quarter video graphics array QVGA grade display, z duck@hanyang.ac.kr to confirm whether simulations can be used to predict the crystallization behavior and device parameters of the arrays over an entire panel. Experimental Figure 1a is a schematic of the FALC process In this technique, an ultrathin layer of Ni catalyst was deposited on an amorphous silicon a-si film, and an electric field or current was applied during crystallization. The configuration of the Ni-FALC poly-si TFT is illustrated in Fig. 1b. A Ni-FALC top-gate poly-si TFT array was fabricated on a 3.6 in mm Corning 1737 glass substrate as follows. The 50 nm thick a-si layer was deposited onto the SiO 2 passivated substrate, and the active layer was defined by a photolithography process. After the gate region of the transistor in the active layer was masked by a 60 nm thick plasma-enhanced chemical vapor deposition PECVD SiO 2 layer, a 1.5 nm thick Ni crystallization catalyst was selectively deposited onto the source and drain regions by sputtering, which was followed by PH 3 doping using an ion mass doping system. Using an optimally designed common electrode mask based on the simulation results, the sources and drains of the transistors in the array were connected to molybdenum common electrodes. To completely crystallize the m channel region in the transistor, samples were annealed in nitrogen ambient at 500 C for 4 h. After the common electrode and the sacrificial layer were etched off, a 100 nm thick SiO 2 gate dielectric was deposited by PECVD at 280 C. Finally, a 300 nm thick Mo gate electrode was deposited and patterned. Results and Discussion Simulation fundamentals. To accomplish uniform crystallization in the a-si array using the FALC process, the entire resistance of the current path has to be understood. We used the Mathcad program to determine the dependence of the resistance on the geometric parameters of metal lines and the number of transistors or a-si cells. The other minor components of resistance in the circuit were ignored to simplify the calculations. In a simple structure consisting of less than four transistors, as shown in Fig. 2, the total resistance of the current path is a sum of the contribution from the a-si cells and the metal lines. According to the simulation, as the number of the a-si cell N increases, the total resistance decreases to R total /N 2, and the governing geometric parameter that determines the total resistance is the number of a-si cells. However, one cannot apply the simple calculation scheme in Fig. 2 to a circuit consisting of more than four a-si cells because

3 H2 Journal of The Electrochemical Society, H1-H Figure 1. Schematic diagram of a the FALC process and b top-gate poly-si TFT fabrication using FALC. there are multiple inputs/outputs at the node in the circuit Fig. 3. The Y-delta transformation is necessary to solve this problem. Furthermore, separate Y-delta transformations of the array rows and columns are necessary to calculate the total resistance in an array of a-si cells. In this study, the Y-delta transformation enabled a reliable and convenient estimation of the resistance in an array. The uniform crystallization of an a-si array after the application of an electric driving force is controlled by the current density rather than the current itself. The current density simulation predicts the overall positional variation in the current density in an array as a function of the initial applied voltage and the geometric simulation parameters, such as thickness, width, and length of the a-si cell or metal line, by calculating the IR drop in the individual resistance components of the equivalent circuit. An assessment of the most favorable process parameters after the simulation was based on the following conditions: i The minimum current density had to be higher than A/cm 2 to induce the FALC effect during crystallization 19 and ii for uniform crystallization, the positional variation in the current density had to be small. Uniform crystallization through optimal design of the current density distribution. To achieve uniform crystallization, the most important factor to consider is the uniform electric current density, which is determined by the resistance components in the current path. To evaluate the uniformity of the current in the array, the DOU was defined as follows current max. current min. DOU % = 100 current min. In this equation, current max. and current min. stand for the maximum current density and the minimum current density in the array, respectively. This simple equation indicates that the uniformity becomes better as the DOU value approaches 0. Preliminary simulations based on the considerations detailed above revealed that the current difference between maximum and minimum values decreased from 120 to 20 A/cm 2 as the length of the a-si cell/channel channel + source/drain offset area increased from 30 to 70 m in a channel of fixed thickness and width. However, the length of the channel should be less than 50 m to maintain the minimum current density requirement of A/cm 2. The simulations indicated that a thick metal line has a favorable effect on the current up to a certain thickness but then does not affect the current beyond that thickness. Figure 4 shows the simulation result of the current density as a function of channel length and metal thickness. All the above simulation results were taken into account when Figure 2. Equivalent circuits of simple structures consisting of less than four a-si cells: a A one-a-si cell structure and b a four-a-si cell structure. Figure 3. Color online Y-delta transformation: The left circuit consists of more than four a-si cells with multiple inputs/ outputs at the node. A separate Y-delta transformation to an array row and a column is required to evaluate R total in a-si cells. The right circuit demonstrates the application of Y-delta transformations.

4 Journal of The Electrochemical Society, H1-H H3 Figure 4. a The simulation result of current density as a function of channel length in an array and b the simulation result of current density as a function of metal thickness. Inset shows the uniformity dependency on the metal thickness. designing the electrode for uniform crystallization. Figure 5a presents a schematic of the electrode mask design and the simulation results of the three-dimensional 3D current density distribution profile obtained from simulations using the mask. The predicted maximum and minimum current densities were and A/cm 2, respectively, and the largest positional variation in the current density was less than 1%. Further studies are underway based on our simulation results to achieve zero positional variation in an array. The actual crystallization of a-si cells was done using the designed mask, and the Raman spectroscopy NRS-3100 analysis was carried out after the crystallization to assess the degree of crystallization DOC. Figure 6a shows overlapping Raman spectra from more than 90 different cells at various positions in the array. All the spectra show a characteristic peak of crystalline Si at 521 cm 1, indicating uniform crystallization over the entire array. Using the data in Fig. 6a, the positional variation in the DOC was plotted and is clearly shown in Fig. 6b. For this 3D profile distribution, peak separation 20 deconvolution was carried out using the Table curve 3D v.4.0 module of the peak fit TM program 4.0. In particular, the poly-si peak at cm 1 reported by Tay et al. 21 was employed in the peak deconvolution process to maximize accuracy in interpreting the DOC. The average DOC was approximately 90%. This positional dependency of the DOC in a panel agreed well with the 3D profile of the simulated current density distribution in Fig. 5b, implying that simulation provides useful information to obtain crystallization uniformity. Figure 5. a A schematic of the electrode mask design and b the simulation results of the 3D current density distribution profile obtained from the mask. Positional variation in device properties. The uniformly crystallized array was further processed for the fabrication of TFTs. All the poly-si TFTs in an array had a channel geometry of 20/20 m width/length with a thickness of 50 nm. The transfer characteristics were measured using an Agilent 5270B instrument under dark conditions. Figure 7 presents the drain current I d vs gate voltage V g characteristics of transistors at a small drain voltage. To evaluate the uniformity in a panel, the array area was divided into 9 subdomains, and 10 randomly selected transistors in each domain were evaluated. The threshold voltage was defined by the transconductance G m method, which determines V th at the maximum derivative of G m given by Eq. 1 g m = I ds 1 V gs and the field-effect mobility and subthreshold swing were deduced from the electrical characteristics in a linear operating region at

5 H4 Journal of The Electrochemical Society, H1-H Table I. Average values and variation in device parameters. Device parameters Average value variation Threshold voltage 5.9 V V Field-effect mobility 92.5 cm 2 /V s cm 2 /V s, 9.8% Subthreshold voltage 0.65 V/decade On/off ratio Figure 6. a Raman spectra from many poly-si cells obtained by FALC at different positions in the panel and b 3D crystallinity distribution of poly-si cells in the array arrows in the figure indicate the direction of the current flow during crystallization. V ds :0.1 V. 22 The 3D profile of the device parameters was obtained by analyzing the 90 data points acquired from the 9 subdomains using Table curve 3D v.4.0. The average values of the device parameters are listed in Table I. All the parameters had good values with an acceptable deviation. Because the completion of device fabrication was performed on a uniformly crystallized array in which we knew the positional variation in the DOC, we investigated the relationship between device properties and the DOC as a function of position. Figure 8 demonstrates the distribution of V th in an array; the arrows in the figure indicate the direction of the current flow during crystallization. V th shows a good uniformity with a deviation of only 0.2 V. For a high resolution display backplane like AMOLED, a subpixel structure of approximately 2Tr + 1Cap per subpixel is required in contrast with active matrix liquid crystal display, where the 2Tr + 1Cap structure is typically required. If the uniformity between transistor properties is not enough to satisfy the AMOLED specifications, then at least two extra transistors are necessary for the compensation circuit. The uniformity of threshold voltages obtained from this current study is therefore highly encouraging. Figure 9a and b is the 3D distribution profiles of channel mobility and subthreshold swing, respectively. As in Fig. 8, the arrows in the figures indicate the direction of current flow during FALC. Although these configurations do not show as close a match with the simulation results as the DOC, there is still a similarity between the transistor parameters of the devices and the simulation results. This may be associated with the influence of the gate dielectric and the processes after crystallization. In particular, the distribution of V th is more or less related to the defects in a dielectric layer. 23 Nevertheless, the variation in the device parameters is reasonably small to meet the requirements for TFTs in an AMOLED backplane. Conclusion In this study, we demonstrated uniform device properties of an LTPS-TFT array that was prepared by an optimized Ni-FALC and the correlation in positional variation between crystallization and device characteristics. To provide uniform electric driving force current density to individual a-si cells, a common electrode design was chosen using Figure 7. Transfer characteristics of the Ni-FALC poly-si TFTs in an array. Figure 8. 3D V th distribution of the Ni-FALC poly-si TFT array the solid arrow is the current in and the dashed arrow is the current out.

6 Journal of The Electrochemical Society, H1-H H5 interface originating from the low temperature oxide. Moreover, an uneven oxide thickness in the array can be an additional factor. With regard to the quality of poly-si by current density control and small positional distribution in the device parameters of optimized poly-si TFTs, the FALC process can be considered as a compatible technique for the AMOLED TFT backplane. Figure 9. 3D distribution of device parameters: a Field-effect mobility and b subthreshold swing the solid arrow is the current in and the dashed arrow is the current out. Mathcad simulation. The LTPS-TFT array, which was fabricated by high quality poly-si, has uniform device parameters such as a threshold voltage of 5.9 V V th = 0.2 V and a field-effect mobility of 92.5 cm 2 V 1 s 1 error variation of 9.8%. The experiment revealed that the 3D profile of crystallinity agrees well with the simulation result. However, a slight deviation between simulation results and profiles of device parameters seems to be associated with the influence of gate dielectric and other fabrication processes after the FALC process. In particular, V th distribution may be attributed to local charges in the gate oxide and Acknowledgments This research was supported by the Korea Research Foundation KRF J04103 and by a grant F from the Information Display Research and Development Center, one of the Knowledge Economy Frontier Research and Development Programs funded by the Ministry of Knowledge Economy of the Korean government. Hanyang University assisted in meeting the publication costs of this article. References 1. W. Benzarti, F. Plais, A. De Luca, and D. Pribat, IEEE Trans. Electron Devices, 51, S.-W. Lee, E. Kim, S.-S. Han, H.-S. Lee, D.-C. Yun, K. M. Lim, M.-S. Yang, and C.-D. Kim, IEEE Electron Device Lett., 24, J. S. Yoo, H. J. Lee, J. Kanicki, C. D. Kim, and I. J. Chung, in Proceedings of the International Display Research Conference, Society for Information Display, p K. H. Kim, S. J. Park, K. S. Cho, W. S. Son, and J. Jang, SID Int. Symp. Digest Tech. Papers, 33, T. Aoyama, G. Kawachi, N. Konishi, T. Suzuki, Y. Okajima, and K. Miyata, J. Electrochem. Soc., 136, S. H. Park, S. I. Jun, K. S. Song, C. K. Kim, and D. K. Choi, Jpn. J. Appl. Phys., Part 2, 38, L A. T. Voutsas, A. M. Marmorstein, and R. Solanki, J. Electrochem. Soc., 146, M. C. Lee, S. M. Han, M. Y. Shin, and M. K. Han, in Proceedings of the International Electron Devices Meeting, IEEE, p J. S. Im, M. A. Crowder, R. S. Sposili, J. P. Leonard, H. J. Kim, J. H. Yoon, V. V. Gupta, H. J. Song, and H. S. Cho, Solid State Phys., 166, M. Hatano, T. Shiba, and M. Ohkura, SID Int. Symp. Digest Tech. Papers, 33, A. K. Kalkan and S. J. Fonash, J. Electrochem. Soc., 144, L S.-W. Lee and S.-K. Joo, IEEE Electron Device Lett., 17, J. C. Kim, J. H. Choi, S. S. Kim, and J. Jang, IEEE Electron Device Lett., 25, Y. B. Kim, C. H. Kim, H. C. Kim, Y. W. Kim, H. P. Jeon, and D. K. Choi, J. Vac. Sci. Technol. B, 23, J. B. Lee, D. K. Choi, and Y. H. Yang, Thin Solid Films, 408, S. Y. Yoon, S. J. Park, H. Kim, and J. Jang, Thin Solid Films, 383, M. A. T. Izmajlowicz, A. J. Flewitt, W. I. Milne, and N. A. Morrison, J. Appl. Phys., 94, D.-K. Choi, H.-C. Kim, and Y.-B. Kim, Appl. Phys. Lett., 87, M. H. Kim, J. H. Jung, S. M. Bobade, D. K. Choi, Y. B. Kim, and J. H. Shin, J. Korean Phys. Soc., To be published. 20. R. Tsu, J. Gonzalez-Hernandez, S. S. Chao, S. C. Lee, and K. Takada, Appl. Phys. Lett., 40, L. Tay, D. J. Lockwood, J. M. Baribeau, X. Wu, and G. I. Sproule, J. Vac. Sci. Technol. A, 22, M. Tsuno, M. Suga, M. Tanaka, M. Mattausch Miura, and M. Hirose, IEEE Trans. Electron Devices, 46, X. Zeng, X. W. Sun, and J. K. O. Sin, Microelectron. Reliab., 44,