Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

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1 Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Li Zheng, Student Member, IEEE, and Muhannad S. Bakir, Senior Member, IEEE Georgia Institute of Technology Atlanta, Georgia, U.S.A. ABSTRACT High-density electrical microbumps (25 µm diameter and 50 µm pitch) and fluidic microbumps are important to support high-bandwidth signaling, power delivery and microfluidic cooling of highperformance high-power chips in 3DICs and silicon interposer. Simultaneous fabrication of electrical and fluidic microbumps is demonstrated in this paper. Test vehicles are also fabricated for assembly. Four-point resistance measurements and preliminary fluidic testing demonstrate assembly results. I. Introduction Three-dimensional ICs are pursued today in the semiconductor industry due to their compelling advantages: higher bandwidth and shorter delay interconnects, smaller form factor, lower signaling power, and heterogeneous integration. However, before one can fully utilize the benefits of 3D integration to stack multiple high-performance processors and memory chips, thermal management and power delivery are two major challenges that must be addressed. Moreover, recently, silicon interposer technology has attracted attention due to its similar advantages as 3D technology and relative ease of implementation. This approach to chip interconnection is also often referred to as 2.5D integration. Xilinx has developed a silicon interposer based FPGA [1] in which multiple dice are placed on a silicon interposer to attain 100X improvement in inter-die bandwidth per watt compared to multichip modules. IBM has also recently demonstrated an 8X10Gb/s I/O system on silicon interposer [2]. The critical components of high-bandwidth silicon interposer technology are fine-pitch electrical microbumps (E-µbumps) and fine-pitch wires. Fabrication, assembly and testing of E-µbumps of 25 µm diameter, 50 µm pitch, and a density of ~40,000/cm 2 are reported in [3], [4]. Fine-pitch E- µbumps not only support large bandwidth, but also support power delivery. Power supply noise (PSN) increases drastically when high-performance processors are stacked. Increasing the number of power/ground pads (bumps) is an effective way to suppress PSN [5]. The cooling of future electronics is also challenging. High-performance processors are projected to dissipate more than 100W/cm 2. A stack of these processors cannot be cooled using conventional forced-air cooling [6]. Microfluidic cooling has been demonstrated as a promising cooling technology for high-performance chip stack [7][8]. Integration of microfluidic cooling into a single or 3D chip-stack raises new challenges to chip I/Os and assembly. The main challenge is that microfluidic I/Os need to be fabricated and assembled along with electrical I/Os to form good electrical and fluidic interconnections. Solder- and polymer-based fluidic I/O technologies have been reported in [6]. Solder-based fluidic I/Os have the advantages of good hermeticity, low moisture absorption, flexibility of I/O height, reworkability and simultaneous fabrication with electrical I/Os. In this work, we demonstrate an I/O technology featuring high density E-µbumps, fluidic microbumps () and fine-pitch wires for silicon interposer and 3D IC technologies. Collectively, these technologies address off-chip signaling, power delivery, and cooling for single and 3D chips on a silicon interposer. The paper is organized as follows: Section II briefly introduces silicon interposer and 3D system with embedded microfluidic cooling. Next, design considerations for E-µbumps and are discussed. Section III describes the simultaneous fabrication of E-µbumps /12/$ IEEE 159

2 and. Section IV presents the assembly and testing results. Finally, Section V is the conclusion. presented in [9] show that increasing the number of power/ground pads help suppress the power supply noise in a 3D chip stack. II. Interface Design Fig. 1(a) is a schematic of a silicon interposer with a pair of processor-memory stack. Note since the processors are liquid cooled, they are located at the bottom most of the stack. Microfluidic vias and channels are fabricated in both the processor and interposer, and are used to interconnect them to form a continuous microfluidic network. Coolant is pumped into the fluidic network to reject the heat from the dice. E-µbumps and fine-pitch wires form the electrical interconnection between two dice assembled on the silicon interposer. In Fig. 1(b), we show a different configuration enabled through the novel cooling and I/Os: a single 3D IC stack containing two processors and a stack of memory chips. While E-µbumps and TSVs provide high-density electrical connectivity, the are used to assemble the fluidic network within the processor stack and the substrate. The simultaneous fabrication and assembly of E- µbumps and enable liquid cooling and dense electrical connectivity. Fig. 1(c) is a top view of an E-µbump array and two rows of. (a) Microfluidic channel Silicon interposer (b) Fine-pitch wires Substrate Memory stack Processor E-µbumps Figure 1: (a) silicon interposer with two processor-memory stacks; (b) 3D processors and memory stack; (c) Top view of F- µbumps and E-µbumps A. Electrical Microbumps Considerations Fine pitch E-µbumps can be utilized towards high bandwidth signaling and power delivery. Analysis performed using compact physical modeling of the power distribution network (c) TSVs Figure 2: Power supply noise vs. Number of power delivery I/Os (4-chip stack with microfluidic cooling, power density of 100w/cm 2 for each chip) Fig. 2 shows the decreasing power supply noise of a 4-chip stack when the total number of power/ground pads and TSVs increase from 2,048 to 18,432. The simulations assume 10:1 aspect ratio TSVs fabricated within a 450 µm thick 1cm 2 die with embedded microfluidic cooling (thinner is possible, and demonstrated in recent work[10]). Each die in the stack is assumed to have 10% of the die area dedicated towards decoupling capacitors and dissipates 100 W of power at a supply voltage of 1 V. In this work, E-µbumps of 25 µm diameter and 50 µm pitch are targeted. The E-µbumps array size is 150 X 150 (total of 22,500 microbumps). B. Fluidic Microbumps Considerations Solder based are chosen for fluidic I/Os due to the advantages mentioned previously. Two rows of are placed on two edges of the chip, as shown in Fig.1(c). The dimensions of the annular shaped are determined by the diameter of fluidic vias and dimensions of the E- µbumps. The inner diameter of should be equal to or larger than the diameter of fluidic vias. Moreover, the number and diameter of fluidic vias are mainly determined by the allowable pressure drop and chip area consumption. For a given flow rate, a smaller pressure drop is preferred of course. It not only improves the reliability, but also saves pumping power. For the microfluidic heat sink of interest, it was reported that the pressure drop is approximately 40 kpa to 80 kpa for a flow rate of 160

3 45 ml/min and 70 ml/min, respectively [8]. In this work, the pressure drop of fluidic vias is assumed to be less than 15 kpa. The total pressure is approximately 120kPa at 70 ml/min. For a given flow rate, one desires the pressure drop to be as small as possible. As to the die area consumption, we assume that it is less than 0.5% of total die area. In Fig. 3, the shaded region corresponds to the design space where vias meet both pressure drop and area consumption requirements. Here, the flow rate is assumed to be 70 ml/min, and the total height of two vias plus the F-bumps in between is 200 µm. measurement results are also listed in table 1, along with the height of E-µbumps, which are simultaneously fabricated. The labeled #3 and #4 in the table yielded the closest height (<1µm difference) after reflow to the E-µbumps. Table 1: Height Experiment Results F-µbump Inner Dia. (µm) Outer Dia. (µm) Height * (µm) # # # # # # E-µbump *Height after solder reflow In this work, we choose F-µbump design #3 in Table 1. Having the E-µbumps to be little higher than the ensures good electrical interconnection. Fig. 4 is an illustration of the dimensions of the E-µbumps,, and fluidic vias used in this work. 25 µm Dia.E-µbumps Inner Dia. 150 µm Outer Dia. 210 µm Figure 3: Pressure Drop and Chip Area Consumption of Fluidic Vias with Different Diameters (Total height is 200µm; flow rate is set to 70mL/min) Fluidic vias of 100 µm diameter are chosen from the design space. The inner diameter of the F- µbumps is chosen to be larger than that of fluidic vias, leaving 20~30µm space to avoid via clogging and to compensate for misalignment during assembly. The outer diameter of is influenced by the diameter of E-µbumps. This is because the electroplating rate is different for the different sized features, and solder reflow also causes the height to change. Experiments were performed to find the size of that leads to with similar height as the 25 µm diameter E-µbumps after electroplating and solder reflow. Height uniformity across the chips is critical to attain reliable fluidic and electrical interconnection. Six different inner diameter and outer diameter combinations for the, as listed in table 1, were fabricated. Details of the fabrication are described in the following section. The height 100 µm Dia. Fluidic via Figure 4: Size comparison of, E-µbumps and fluidic via. III. Simultaneous Fabrication of E-µbumps and Wafer-level simultaneous fabrication of E- µbumps and is reported in this section. In our experiments, a double side-polished 4-inch wafer was the starting point. First, a 3 µm thick layer of SiO 2 is deposited (Fig. 5(a)). Next, a seed layer is sputtered on the oxide film. The seed layer consists of a thin layer of titanium (300Å) on copper (2000Å). The Ti layer improves the adhesion of the copper layer to oxide layer. The next step is to pattern fine pitch wires and copper pads for the E- µbumps and. Circular- and annularshaped pads are patterned for the E-µbumps and, respectively. Fine-pitch wires and pads are electroplated (Fig. 5(b)). After copper electroplating, a thick resist mold is patterned above the copper pads to electroplate Ni as an under bump metallization (UBM). Eutectic solder (60%/40% tin-lead in this work) is plated above the 161

4 Ni. Following electroplating, the removed. The final step is to reflow 6 is an SEM image of, fine-pitch wires (8 µm wide, interconnecting the E-µbumps. seed layer is the solder. Fig. E-µbumps and 2 µm thick) Table 2: Chip Parameters and Bonding Profile Chip parameters Die size ~1cm X 1cm Number of E-µbumps 22,500 (150X150) Number of F- µbumps 42 (2 rows) E-µbumps dimensions Diameter = 25µm; height = ~12µm dimension Inner Dia. = 150µm; Outer Dia. = 210 µm; Height = ~12µm Bonding profile Temperature ramp 2oC/sec Peak temperature 230 oc Peak temperature 15sec duration Force applied 5~10N (a) Silicon wafer with 3µm oxide Pads for E-µbumps Pads for E-µbumps (b) Copper pads are electroplated up for E-µbumps and Fµbumps (c) Solder reflow after nickel and solder plating (a) (b) Figure 5: Simultaneous fabrication of E-µbumps and (wires are not shown here) Figure 8: IR image of (a) ; (b) E-µbumps and fine wires F-µbump Fine-pitch wire Applying the bonding parameters listed in Table 2, and E-µbumps are bonded simultaneously. Fig. 8 illustrates IR images after flip-chip bonding. From the images, good alignment is visually clear. E-µbump Figure 6: SEM of E-µbumps and after solder reflow A. Testing After flip-chip bonding, the resistance of single E-µbumps is measured. The 4-point resistance measurement setup is shown in Fig. 9. IV. Assembly and Testing A. Flip-chip Bonding Test vehicles for assembly and testing are fabricated using the processes described in section III. Flip-chip bonding is used to assemble chips to a silicon interposer. The assembled chips contain Fµbumps, E-µbumps and fine-pitch wires, as shown in Fig. 6, while the substrate only contain copper pads. Fig. 7 illustrates the flip-chip bonding process. Chip Substrate Wires on chip E-µbump under test Wires and probe pads on substrate Figure 9: 4-point resistance measurement for one E-µbump E-µbumps Three E-µbumps are interconnected using fine-pitch wires on the chip and substrate to yield the measured resistance of the E-µbump under test. In Figure 7: Flip-chip bonding of E-µbumps and 162

5 Fig. 9, the red traces denote the current flow, and the blue traces denote the voltage drop measurement (sense). Eight E-µbumps are measured, as shown in Fig. 10, for three different chips. The average resistance is mω, and the standard deviation is 1.82 mω. These numbers agree with the resistance measurements reported in [3]. In Fig. 11(a), the left F-µbump has a bubble inside, which indicates poor sealing. On the other hand, the right F-µbump has no bubble, which indicates good sealing. After increasing bonding force from 5N to 10N, no bubbles were found, as shown in Fig. 11(b), indicating improvement in the bonding of the microfluidic I/Os. V. Conclusion An I/O technology featuring and high density E-µbumps is demonstrated. High density Eµbumps are indispensable to 3D IC and silicon interposer integration since they drastically improve the signaling bandwidth and suppress the power delivery noise. Solder based are designed as a fluidic interface between dice and interposer due to their good fluidic sealing, ease of fabrication and assembly, and other aforementioned advantages. Moreover, simultaneously fabrication and assembly of Eµbumps and simplify the fabrication process. Test vehicles are fabricated and assembled. Following assembly, resistance of a single E-µbump is measured using 4-point method. Average resistance is mω. Preliminary fluidic testing demonstrates good bonding of. Future work includes fabrication of fluidic vias and microchannels, and demonstration of a complete microfluidic network. Figure 10: Resistances of a single E-bump Fluidic sealing of the F-µbump after bonding is visually and preliminary tested in this work. The bonded samples are dipped into water. If there are voids in the after assembly, water flows inside (i.e., air escapes), possibly forming trapped air bubbles, as shown in Fig. 11(a). (a) Trapped air bubble Reference [1] N. Kim, D. Wu, D. Kim, A. Rahman, and P. Wu, Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV), 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), pp , May [2] T. O. Dickson et al., An 8x10-Gb/s SourceSynchronous I/O System Based on High-Density Silicon Carrier Interconnects, in Proc. IEEE VLSI, 2011, pp [3] S. L. Wright et al., Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications, in th Electronic Components and Technology Conference, 2006, pp [4] J. Maria et al., 3D Chip Stacking with 50 µm Pitch Lead-Free Micro-C4 Interconnections, in st Electronic Components and Technology Conference, 2011, pp No bubble was found after increasing bonding force from 5N to 10N. (b) Figure 11: Fluidic sealing testing: (a) trapped air bubble indicates bad sealing. (b) No bubble was found after increasing bonding force to 10N. 163

6 [5] L. Zheng, Y. Zhang, G. Huang, and M. S. Bakir, Power delivery and thermal management for highperformance 3D chip stack, in TECHCON, [6] C. R. King, J. Zaveri, M. S. Bakir, and J. D. Meindl, Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), pp , [7] B. Dang, M. Bakir, and J. D. Meindl, Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink, Electron Device Letters, IEEE, vol. 27, no. 2, pp , [8] Y. Zhang et al., Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology, in st Electronic Components and Technology Conference, 2011, pp [9] G. Huang, M. Bakir, A. Naeemi, and J. D. Meindl, Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication, IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp , [10] Y. Zhang, A. Dembla, Y. Joshi, and M. S. Bakir, 3D Stacked Microfluidic Cooling for High-Performance 3D ICs, in nd Electronic Components and Technology Conference,