Lecture 3: Integrated Processes

Transcription

1 Lecture 3: Integrated Processes Single-Crystal Silicon Process Integration Polysilicon Micromachining Process Integrated CMOS Micromachining Process ENE 5400, Spring Single Crystal Silicon ENE 5400, Spring

2 Silicon a/2 ENE 5400, Spring Crystal Directions Directions given in x, y, and z vectors Planes described by Miller indices: directions of vectors orthogonal to the planes z y x ENE 5400, Spring

3 Crystal Planes Individual planes denoted by parenthesis (x,y,z) Negative plane intercepts denoted by x z (100) plane (100) plane y x ENE 5400, Spring Equivalent Crystal Planes Equivalent crystal planes denoted by curly bracket {x,y,z} For example {100} has six equivalent planes z (100) plane {100} planes y (100) plane (010) plane ENE 5400, Spring x 3

4 Other Planes z (221) plane y x ENE 5400, Spring Crystal Directions Individual directions denoted by square bracket [x,y,z], which is perpendicular to the corresponding plane (x,y,z) z [100] direction (100) plane y (100) plane ENE 5400, Spring x [100] direction 4

5 Equivalent Crystal Directions Equivalent directions denoted by angular brackets <x,y,z> z [100] direction <100> directions (100) plane y (100) plane x [100] direction ENE 5400, Spring Vector Algebra and Intersections of Planes Given to planes with the directions u and v, what is the angle between them? cosθ = u v u v What is the angle between planes with the corresponding vectors [100] and [110]? Ans: 45 ENE 5400, Spring

6 Wafers Identified by coded Flats ENE 5400, Spring (100) Wafer and its Relevant Planes (100) wafer Source: M. Madou, Fundamentals of Microfabrication, CRC Press, 1997 ENE 5400, Spring

7 Plane Orientation to Wafers ENE 5400, Spring Plane Orientation to Wafers? A {100} plane ENE 5400, Spring

8 Etching z x Mask aligned to {110} primary flat y {110} primary flat ENE 5400, Spring Etching z x y What are the angles of the pit wall relative to the Surface of the wafer? Ans: ENE 5400, Spring

9 Wet Etching ENE 5400, Spring Anisotropic Si Etch ENE 5400, Spring

10 Undercut of Non-{110} Aligned Masks Rotated features on masks expose planes that etch rapidly Features stop on {110} planes circumscribed around mask {100} {100} ENE 5400, Spring V-Groove for Optical Fiber Alignment < 1 µm tolerance ENE 5400, Spring

11 Integration: Process Design Issues Device Geometry Manufacturability: critical dimensions, uniformity, and variation Sizing; big or small System Partitioning Monolithic integration Multi-chip modules System Package Encapsulation needed? Environmental access? Process Partitioning Frond-end process (includes all of high-temperature steps) and back-end process (interconnect and packaging)» Contamination separate IC and MEMS steps (e.g., Au and Cu can rapidly diffuse into silicon) ENE 5400, Spring More Process Design Issues Thermal Constraints Compatibility (e.g., the oxide deposited after metal should be PECVD or other low-temperature process) Diffusion effect: dopant, metal/si interface Morphology Residual stress Material Properties Stress control Stiffness Mechanical stability of interim structures; buckle and fracture Interconnect Die Separation; encapsulation of movable parts on wafer level ENE 5400, Spring

12 Example: Single Crystal Reactive Etching And Metallization (SCREAM) Ref: N.C. MacDonald, Sensors and Actuators A, vol. 40, no. 1, pp , 1994 suspended beam photoresist oxide (1) Deposit PR and oxide (4) Coat sidewalls with PECVD oxide (7) Al sputtering for electrical interconnect (2) Lithography and oxide etch (5) Remove oxide at bottom And etch Si (3) Anisotropic Si etch (6) SF 6 plasma etch to ENE 5400, Spring 2004 release structures 23 Silicon Fusion Bonding with Reactive Ion Etching High aspect ratio microstructures photoresist oxide silicon PR silicon (1) Deposit PR and oxide silicon (4) Si fusion bonding silicon (6) Lithography suspended beam (2) Lithography and oxide etch (3) Etch cavity (5) CMOS fabrication ENE 5400, Spring silicon silicon (6) Deep silicon RIE 12

13 Thick Polysilicon Process by Robert Bosch Uses surface/bulk micromachining techniques for inertial sensor fabrication aluminum 12 um n+ epi poly-si SiO 2 suspended device silicon (1) Deposit SiO 2 and poly-si; Deposit and pattern Al (3) Two deep RIE of Si; Sacrificial etch of SiO 2 cap 50 um (2) Anisotropic Si etch; Pattern and etch poly-si *Lutz et al., int. conf. on Solid-State Sensors and Actuators, 1997 ENE 5400, Spring glass (4) Bond cap wafer; anodic bond glass Dissolved Wafer Process Uses wet etching for low-cost applications silicon (1) Etch recess by RIE or wet etch #7740 glass (4) Fusion bonding (2) Diffuse boron #7740 glass (5) Wafer etch in EDP (3) Pattern structure by RIE * Cho, Proc. of SPIE, 1995 * K.D. Wise, IEEE Trans. Electron Devices, vol. 49, no. 1, pp , 2002 ENE 5400, Spring

14 HEXSIL Process (1) Deep Si plasma etch (4) Lap and polish Poly-Si (2) Sacrificial SiO 2 deposition (5) Poly-Si deposition and patterning (3) Poly-Si deposition and pattering (6) HF etch release * C. Keller and M. Ferrari, Hilton Head, 1994 ENE 5400, Spring HEXSIL Structure Micro-gripper From C. Keller (in Madou s book) ENE 5400, Spring

15 Lithographie, Galvanoformung, Abformung (LIGA) Process Developed in Karlsruhe, Germany; very high aspect ratio features (> 100) achieved by lithography, electroplating and molding x-ray mask synchrotron radiation polymethyl methacrylate (PMMA) (1) exposure (3) electroplating (2) developed PMMA ENE 5400, Spring (4) PMMA removal Polysilicon Micromachining Process ENE 5400, Spring

16 MUMPs Process Flow Multi-User MEMS Processes; developed at Berkeley Sensors and Actuators Center (BSAC) in the late 80 s A well-known commercial three-layer Poly-Si surface micromachining process run by Cronos Intrgrated Microsystem, a JDS Uniphase company (1) Deposit LPCVD silicon nitride and Poly-Si; coat photoresist *D. Koester et al., MUMPs Design Hankbook, 2001 ENE 5400, Spring MUMPs Process Flow (2) lithography; pattern photoresist (3) RIE of Poly-Si; strip PR in a solvent bath (4) Sacrificial LPCVD oxide (PSG) ENE 5400, Spring

17 MUMPs Process Flow (5) Dimples; RIE of oxide using PR as mask (6) Anchor 1; RIE of oxide using PR as mask (7) Undoped Poly-Si by LPCVD; deposit PSG; anneal at 1050 C ENE 5400, Spring MUMPs Process Flow (8) Etch PSG with PR as mask; RIE of Poly 1 with PSG as mask (9) 2nd oxide (PSG) (10) P1_P2_Via;RIE of 2nd oxide with PR as mask ENE 5400, Spring

18 MUMPs Process Flow Anchor 2 Etch (10) Anchor 2; RIE of 2nd oxide with PR as mask (11) Undoped Poly2 by LPCVD; deposit PSG; anneal at 1050 C (12) Etch PSG with PR as mask; RIE of Poly 1 with PSG as mask ENE 5400, Spring MUMPs Process Flow (13) Deposit gold; patterned by lift-off (14) Release oxide etch in 49% HF ENE 5400, Spring

19 MUMPs Layers ENE 5400, Spring Stress Control of Polysilicon As-deposited highly-doped polysilicon films have a large compressive stress and a large stress gradient through the film thickness, causing microstructures to buckle and deflect out of plane Residual stress and stress gradients can be greatly reduced by annealing at temperature above 1000 C for 1 hour CMOS circuits and PSG/nitride contacts cannot survive this long; instead Rapid-Thermal Annealing (RTA) can be applied Source: G.K. Fedder, Ph.D. dissertation, UC Berkeley, 1994 ENE 5400, Spring

20 MUMPs Mask Convention Why do we need hole layers? ENE 5400, Spring MUMPs Design Rules I CIF and GDSII are commonly used file formats submitted to foundry Use minimum feature and space when absolutely necessary ENE 5400, Spring

21 Some MUMPs Design Rules A, B, C, and D all have minimum requirements ENE 5400, Spring CMOS-MEMS Integrated CMOS Micromachining Process: Pre-CMOS, intermediate CMOS, and Post-CMOS Advantages» Low cost in large production volume» Enhanced performance and more functions» Digital interface and programming Disadvantages» MEMS process must be compatible with IC processes» Micromechanical design may be less than optimum» Access to CMOS foundry process?» Photo-lithography for CMOS-MEMS structures? ENE 5400, Spring

22 Complementary Metal Oxide Semiconductor (CMOS) Process CMOS material for MEMS: Silicon Dielectrics: silicon dioxide, silicon nitride, low-k dielectric material Metallization: aluminum, copper, tungsten G D S SiO 2 Poly-Si Source Gate Drain n+ n+ silicon dielectric layers metal (Al) n-channel MOS transistor ENE 5400, Spring Sandia National Lab s imems MEMS parts formed before CMOS no high-temp processes during CMOS MEMS Steps: (1). Etch deep trench (2). Fabricate MEMS devices (3). Refill sacrificial oxide (4) CMP (5) sealed with a nitride membrane 1.25 um CMOS + 1 structural polysilicon (+ 1 interconnect) *image from SNL 3-axis Accelerometer M. Lamkin of UCB, ISSCC 1997 ENE 5400, Spring

23 Modular Integration of CMOS and microstructures (MICS) process Developed in UC Berkeley by R. Howe s group Post-CMOS process; 3 µm CMOS + maximum 2 structural polysilicon Tungsten metallization with TiSi 2 drain/source contact barriers, rather than aluminum max. post-processing temperature up to 835 C (400 C for Al) P-doped LPCVD polysilicon deposition temperature = 610 C; Rapid Thermal Anneal (RTA) at 950 C for 60 seconds MEMS CMOS * From C. T.-C. Nguyen, IEDM, 1993 ENE 5400, Spring MICS Polysilicon Structure CMOS Micromechanical resonator oscillator anchor comb drive anchor Clark T.-C. Nguyen and Roger Howe, IEEE Int. Electron Devices Meeting, 1993 ENE 5400, Spring

24 Polycrystalline Silicon Germanium Semiconductor alloy High-Q (quality-factor) material for radio-frequency (RF) application (e.g. on-chip micromechanical filters) Conventional LPCVD III B Al Ga IV C Si Ge V N P As ENE 5400, Spring Poly-SiGe MEMS after CMOS UC Berkeley CMOS with aluminum metallization Post-CMOS temperature 450 C 90 C H 2 O 2 structural release ENE 5400, Spring Source: Roger Howe 24

25 SiGe-CMOS Structure Stacked resonator on amplifier circuits Andrea Franke et al., Hilton Head, 2000 ENE 5400, Spring High-Q SiGe Structure S.A. Bhave et al., Hilton Head, 2003 ENE 5400, Spring

26 Stress on SiGe Structure Before RTA After RTA ENE 5400, Spring Microstructures Built on Top of CMOS Additional thin film deposition and pattering after completion of CMOS Digital Micromirror Device (DMD), Texas Instrument ENE 5400, Spring

27 CMOS-MEMS at ETH (H. Baltes Group) Post-CMOS release of membrane-type structures by back-side anisotropic Si etch using KOH Must protect front-side Al metallization Alternative: an n-well can be used as electrochemical etch stop dielectric passivation silicon membrane * N. Kerness et al., calorimetric chemical sensor, MEMS 2000 ENE 5400, Spring Sacrificial ALuminum Etching (SALE) O. Paul et al., Sacrificial aluminum etching for CMOS microstructures, MEMS 1997 Stacked metal layers and via and pad opening provide access ports for etching and undercutting structures Dielectric etch stop; excellent selectivity by wet etch Can do vertical electrostatic actuation and capacitive sensing Stacked vias may violate CMOS design rules aluminum dielectric layers silicon Before SALE ENE 5400, Spring silicon After SALE 27

28 CMOS-MEMS at Carnegie Mellon Univ. Maskless; top metallization layer as the etch resistant mask to protect circuits Two-step post-cmos etch: Anisotropic dielectric RIE Isotropic Si etch to undercut structures Reduced parasitic capacitance for capacitive sensing CMOS region microstructural region silicon substrate (1) Die from foundry metallization layers dielectric layers gate poly-si metal mask (2) Oxide etch Released beams ENE 5400, Spring (3) Si etch G. Fedder et al., Sensors and Actuators A v.56, no.2, 1996 CMU CMOS-MEMS Devices Accelerometer IR Imager RF Spiral Inductor Microphone/Microspeaker Mechanical BP Filter Scanning Mirror ENE 5400, Spring

29 CMOS-MEMS Path to Production HP 0.35 µm 4-metal AMS 0.6 µm 3-metal ENE 5400, Spring UMC 0.18 µm 6-metal Cu Multi-Layer Microstructures 14 different permutations with 3 metal and 1 polysilicon layers On field oxide or gate oxide (add diffusion mask) Use of gate oxide results in thinner beams Gate poly + gate oxide not allowed by design rules 7 different permutations 14, on field oxide 7, on gate oxide ENE 5400, Spring

30 Minimum Structural Width Minimum structural width = 1.2 µm; however most CMOS metal design rules are under 1.2 µm Constrained by micromachined dielectric etch, which mills away top metal ENE 5400, Spring Maximum Structural Width Maximum structural width = 20 µm Constrained by micromachined lateral undercut ENE 5400, Spring

31 Minimum Inter-structural Gap Minimum inter-structural gap = 1.2 µm Constrained by micromachined dielectric etch Possibly constrained by metal to metal spacing design rule in CMOS; however most CMOS metal spacing design rules are under 1.2 µm gap insufficient gap ENE 5400, Spring Minimum Structural Metal Extension Minimum structural metal extension = 0.3 µm Constrained by misalignment of metal layers; can cause structures to become disconnected ENE 5400, Spring

32 Minimum Polysilicon Enclosure Minimum polysilicon enclosure = 0.6 µm Protects polysilicon from silicon etching during micromachining process Constrained by misalignment of polysilicon to metal mask ENE 5400, Spring Minimum Electronics Spacing from Edge Minimum electronics spacing from edge = 30 µm Constrained by micromachined lateral silicon etch ENE 5400, Spring