Device and Process Integration Challenges for Thin Film Transistors

Transcription

1 Device and Process Integration Challenges for Thin Film Transistors Arokia Nathan Electrical and Computer Eng., University of Waterloo Waterloo, Ontario, NL 3G1, Canada *currently on leave at Dept. of Engineering, University of Cambridge, UK Can we spread electronics at the nano-scale over large surfaces to monitor/control/modify surface characteristics in an integrated fashion?

2 Acknowledgements Profs. Bill Milne, John Robertson, Gehan Amaratunga, Cambridge University Prof. Denis Striakhilev, Dr. Yuriy Vygranenko, Sanjiv Sambandan, Shahin J. Ashtiani, Stefan Alexander, Reza Chaji, Rick Huang, Clement Ng, Alex Wang, University of Waterloo, Canada Dr. Bob Reuss, Program Manager, DARPA Microsystems Technology Prof. Ghassan Jabbour, Flexible Display Center, Army Research Labs., Arizona State University Prof. John Rowlands, Sunnybrook/University of Toronto Prof. Safa Kasap, University of Saskatchewan Paul Arsenault, Corbin Church, IGNIS Innovation Inc., Canada Dr. Mike Hack, UDC, USA

3 OUTLINE Large Area Electronics applications, material technologies, active matrix Thin Film Transistor Scaling lateral and vertical TFTs, lithography constraints Nano-scale Vertical Transistors anisotropic etching, output characteristics Nano-crystalline Si crystallinity, microstructure, composition High-mobility Ambipolar TFTs silicided contacts, N- and P-channel TFTs, inverter Conclusions

4 Technologies for Large Area Electronics Requirements Low processing temperature: ~300 C glass, ~350 C metal foils, ~150 C plastic. TFTs with low leakage current, high ON/OFF ratio, low voltage operation, and small area. High uniformity/ device matching, high stability and lifetime. Attribute a-si:h nc-si:h poly-si organic Circuit type NMOS NMOS/PMOS NMOS/PMOS PMOS Mobility (µ) low much higher than a-si:h high low Drive capacity (I ON ) large W/L to reduce V G small W/L at small V G small W/L at small V G large W/L to reduce V G Stability (ΔV T ) issue more stable than a-si:h stable improving V T uniformity high high improving improving Mobility uniformity high potentially high improving improving Compensation circuitry for lifetime/non-uniformity yes yes yes yes Manufacturability mature RF PECVD? new has potential Cost low low high potentially low Flexible substrate promising promising uncertain promising Drivers Active matrix organic light emitting diode displays (AMOLEDs) and bio-medical imagers RF ID tags and smart cards

5 Active Matrix Arrays Addressing Circuit Read-out / Driver Circuit flat panel x-ray imager 14.1 fully-compensated AMOLED display Sensor or OLED Data Lines TFT circuit Address Lines eventually flexible... V + Imaging Pixel Detector signal TFT Data Line V + Display Pixel anode OLED cathode signal TFT1 TFT Data Line C s C s V - Address Line V - V - Address Line

6 Thin Film Transistor and Scaling Issues Drive current and transconductance: 1 W IDS = μfeci ( VG VT ) L I DS W gm = = μfeci( VG VT) V L G need W/L >> 1 but (W.L) small, µ FE : material attribute Unity gain frequency: Need to increase f T! f T = glass drain metal gm π ( C + C ) L = 5-10 μm n+ n+ insulator undoped a-si:h insulator gate metal Lateral TFT source metal Decrease channel length, L - but nano-scale lithography is not feasible! Can we use the highly controllable thickness of thin films to define channel length! Vertical thin film transistors? Increase µ FE can material be nano-engineered to improve structural order! Nanocrystalline silicon? gs gd

7 gate metal insulator undoped a-si:h L = m μ VTFT Evolution VMOS - for high current, high power applications Holmes and Salama, Solid State Electron., 1974 VTFT - for high switching speed applications drain M metal n+ insulator Uchida, Nara, Matsumura, IEEE EDL, vol. 5, 1984 n+ source metal glass Vertical TFT

8 i a-si:h i poly-si i poly-si i a-si:h L Drain M M n+ SiN x n+ Source M Glass Source M n+ poly-si SiN x M Gate Uchida, Nara, Matsumura (1984) High contact resistance S/D alignment issues with multiple RIE VTFT Structures Channel = L h + L v Gate Drain M Drain Drain n+ M i a-si:h M M p+ n+ n+ L block v layer Source n+ M poly-si n+ L L SiO h Glass I Gate M Hack, Shaw, Shur (1988) High leakage current - poor gate control in vertical a-si region SiO n+ Source n-type Si substrate Zhao, Cao, Saraswat, Plummer (1994) 600 C poly-si/lto deposition with ion implanted S/D Gate M SiN x L Drain M n+ poly-si Glass Saitoh and Matsumura (1997) Lightly doped a-si layer with ELA S/D High leakage current Chan, Nathan (005) µc-si S/D contacts S/D alignment single RIE Hidden in an active matrix Stutzmann, Friend, Sirringhaus (003) Organic TFTs with channels mirocut by embossing

9 D G S Data lines (source) High Aperture Ratio Pixels lateral vs vertical L g Gate lines Ls pixel electrode (drain) gate 65 μm W TFT Lpa Lp source LTFT VTFT L pa L p Lateral lateral TFT pa TFT TFT pa Pixel Fill Factor: f = Lp Lp f 85% for VTFT with 5-micron design rules Can meet detection specs for mammography! L ( L 5 μm W ) L

10 Vertical TFT Fabrication a-sin :H x n + μc-si or a-si Cr Glass a-sin :H x Cr + n μc-si or a-si Cr a-sin :H x undoped a-si:h Drain Al Cr a-sin :H x Glass 50 nm 100 nm 100 or 50 nm 50 nm 100 nm 300 nm Channel 0.1 or 1 μm 300 nm 100 nm a-sin x:h Cr a-sin x:h undoped a-si:h Cr Gate 1 μm Al n + μc-si or a-si Source

11 Vertical Profile Requirements Isotropic Etching Anisotropic Etching Pure SF 6, 60s over-etch (a) Photoresist Mo n + a-si:h E V E L E V Substrate a-sin x :H Etching of a Substrate Material n + a-si:h (b) SF 6 /O : 50/50, 30s over-etch Multiple Films Photoresist Substrate Substrate Mo n + a-si:h Etching of Multiple Films (endpoint: one possiple case) a-sin x :H Multiple Films n + a-si:h Substrate Substrate Etching of Multiple Films (endpoint: another possible case)

12 Anisotropic Reactive Ion Etching (RIE) CF 4 /H RIE process Cr n + a-si:h a-sin x :H n + a-si:h 100 nm 300 nm 1 μm 300 nm Vertical profile CFx polymer (3) Glass CF 4 CF x CF x (4) e- HF CF 3 + (1) () F SiF x layer a-si:h e- H H F - SiF 4 CFx polymer (1) Ion-assisted etching (3) Polymer deposition on vertical surface () H scavanges F density (4) Sputter removal of polymer from horizontal surface

13 Vertical Thin Film Transistor Structural attributes All the films in multilayer vertical structure are fully self-aligned. Channel length can be precisely defined nm in this case but can be scaled down. Process attributes Semiconductor and dielectric films by PECVD; metal films by sputter deposition. Vertical channel by RIE. a - SiN x :H Cr a - SiN x :H un. a- Si :H Cr n + a - Si :H a - SiN x :H n + a - Si :H Cr (Values in nm) 400 Source Drain 00 Gate Chan, Nathan, APL, vol. 86 (005) Channel

14 I D (A) n + μc-si:h Transfer and I-V Characteristics W/L = 11/0.1 (μm) t SiNx = 50 nm (1 V/step) V D (V) μ FE = 0.05 cm /Vs At V D = 1.5 V: I OFF = A ON/OFF ratio > 10 8 V T =.8 V S = 0.8 V/dec V DS = 0.5 V V G (V) ON/OFF Current Ratio ON Current (μa) OFF Current (fa) Threshold Voltage (V) Sub-threshold Slope (V/dec) I D (μa) W/L = 11/0.1 (μm) t SiNx = 50 nm n + μc-si:h Values > 10 8 > 10 ~1 ~.8 ~0.8 V D (V) I D (μa) V G (V) W = 100/1 (μm) t SiNx = 50 nm n + μc-si:h V G (V) V D (V)

15 VTFT Short Channel Issues Lack of Gate Control Interface Potential [V] Front Back t SiNx:H = 50 nm V D = 0.1 V V D = 10 V V G = 0 V t a-si = 5 nm L=100 nm Normalized Distance from Drain Interface Potential [V] Front Back t SiNx:H = 50 nm V D = 0.1 V V D = 10 V V G = 1 V t a-si = 5 nm L=100 nm Normalized Distance from Drain Possible Solutions Decrease gate dielectric thickness for better gate control - C gate, I gate! Use double gate structure and ground nd gate Sandwich a p+ layer to n+ S/D halo doping Drain Current (μa) W/L = 100/0.1 (μm) V G (V) 30 t SiNx = 50 nm n + μc-si:h Drain Voltage (V)

16 C-V and NMOS Inverter Characteristics VTFT top view Total gate overlap area Source 10 μm Vertical Channel W/L = 0/0.1 (μm) Gate Drain μm μm/div V in V DD T1 T V out NMOS VTFT inverter Total Gate Input Capacitance (ff) TFT size: 10 μm x 10 μm W/L = 0/0.1 (μm) t SiNx = 15 nm n + μc-si:h Lateral TFT 3 µm DR C G-SD ~ 15 pf C G-SD = 48 ff 10 khz AC signal 100 khz Gate Voltage (V) Output Voltage, V out (V) V DD = 4 (V) 3 1 W/L = 40/0.1 (μm) Input Voltage, V in (V)

17 The Quest for High Mobility! Need high mobility TFTs for high frame-rate and thin film CMOS peripheral drivers for eventual system-on-panel integration State-of-the-art devices - re-crystallized poly-si TFTs In a-si:h TFTs, field effect mobility is fundamentally limited and too low (1- cm V -1 s -1 for electrons, 0.01 cm V -1 s -1 for holes); Poly-Si devices have higher field effect mobility ( cm V -1 s -1 for electrons, cm V -1 s -1 for holes) but costly and complex processing and large area non-uniformity in µ, V T. Alternative - direct deposition of nc-si:h thin films Princeton (Wagner et al.) and Cambridge (Milne et al.) cm V -1 s -1 electron field effect mobility has been achieved in lab TFTs. Use of thick ( 700 nm) nc-si:h layer and high temperature ( 400 C). Use of non-conventional deposition techniques (ECR-CVD, VHF-PECVD). Why not conventional RF PECVD for nc-si:h films? High density of defects and high oxygen incorporation at the grain boundaries.

18 REQUIREMENTS FOR HIGH MOBILITY Low defect density & high crystallinity channel Thin incubation layer for bottom gate TFTs High surface smoothness channel for top-gate TFT Thin channel layers to reduce series resistance High conductivity contact layers to reduce S/D contact resistance High quality gate dielectric with good interface integrity S D Steady state Growth phase Nucleation phase Incubation layer Substrate Gate Metal Gate Dielectric Gate Dielectric Gate Metal Substrate Bottom-gate TFTs - lower mobility (quasi a-si:h structure) S Substrate Top-gate TFTs - higher mobility (quasi poly-si structure) If grain size << channel length Uniform device characteristics (V T, I ON, I OFF, µ FE ) over large area. But will we get sufficient grain boundary passivation? D

19 PECVD nc-si:h Films: Growth Rate and Crystallinity Growth Rate (nm/min) nm thick film Standard MHz PlasmaTherm H / (SiH 4 + H ) (%) Crystalline Volume Fraction (%) Dark Conductivity (S/cm) 10-5 H /(SiH 4 + H )=99 % Intensity (a.u.) <111> <> 300 nm nc-si:h grain size 5-30 nm Degree (θ) Film Thickness (nm) 99 % dilution, growth rate.7 nm/min, X c 80 8 % σ dark ~10-6 S/cm, X c ~85 % Crystalline Volume Fraction (%) High density of atomic hydrogen in the plasma favors etching weak Si-Si bonds. High hydrogen surface coverage promotes structural ordering onto stable nucleation sites at the growth surface. Controlled dep of high h crystallinity thin nc-si:h film seems achievable! Lee et al., APL, vol. 86 (005) 106 and Virtual J. Nanoscale Science & Technology vol. 11, 005

20 RF PECVD nc-si:h Film Microstructure TEM Cross-Section Dense columnarlike growth Amorphous incubation layer (~5nm) Glass substrate Normalized Intensity (a.u.) Raman Spectrum H / (H + SiH 4 )= 99 % Raman crystallinity ~ 85 % film thickness ~ 300 nm nano phase ~500 cm -1 amorphous phase ~480 cm -1 crystalline phase ~50 cm Raman Shift (cm -1 ) Electron diffraction patterns - central bright circular region <111> and <0> rings and weak <311> rings with diffraction spots. TEM, Raman and XRD all confirm high crystallinity

21 RF PECVD nc-si:h Film Composition nc-si:h film c-si substrate 10 H /(SiH 4 + H ) = 99 % Concentration (at./cm 3 ) Hydrogen Oxygen Depth (nm) Hydrogen concentration ~ 1.5x10 1 cm -3 Oxygen concentration ~10 17 cm -3 (comparable to UHV deposition) Surface RMS roughness ~33 Å (for 100 nm thick film) Grain size ~ tens of nm, and reasonably uniform Hydrogen also appears to passivate grain boundary defects and thus prevents oxygen incorporation leading to high purity nc-si:h

22 Top Gate nc-si:h TFTs with a-sio x Drain-Source Current ( μa ) P-channel TFT V DS = - 3 V W / L = 00 μm / 50 μm V DS = - 5 V V DS = - 4 V Drain-Source Voltage (V) Drain-Source Current (μa) N-channel TFT W / L = 00 μm / 50 μm V GS = 5 V VGS = 4 V V GS = 3 V Drain-Source Voltage (V) 300 nm 300 nm 90 nm Al Al 50 nm nc-si:h/cr Al S/D silicided a-sio ohmic contact x nc-si:h glass Onset of lateral p-n diode formation at V DS > V GS - V T Source holes Cr Gate Al a-siox nc-si:h electrons Cr Drain

23 TFT Transfer Characteristics Drain-Source Current (A) 10-4 W / L = 00 μm / 50 μm V DS = 1 V NMOS Gate-Source Voltage (V) μ efe ~150 cm /Vs V T ~1.8 V S ~0.3 V/dec Field-Effect g Mobility (cm m L/(WC OX V DS ) (cm /Vs) / Vs) Source-Drain Current ( A ) W / L = 00 μm / 50 μm V SD DS = -1 V PMOS Gate-Drain Voltage (V) μ hfe ~5 cm /Vs V T ~ -3.8 V S ~0.5 V/dec Field-Effect g Mobility (cm m L/(WC OX V DS ) (cm /Vs) /Vs)

24 CMOS Inverter Output Voltage (V) PMOS: 00µm/50µm NMOS: 00µm/100µm V DD = 8 V Output Voltage Gain V IN V DD P N V OUT Input Voltage (V) 0 V SS Output voltage gain: 7.

25 Conclusions Vertical thin film transistors based on a well-defined and reproducible vertical device structure: ON/OFF current ratio ~10 8, threshold voltage ~.8V, and sub-threshold slope of ~0.8 V/dec. Device can be easily scaled to sub-100 nm channel lengths but need device optimization to reduce short channel effects. Direct deposition of nc-si:h using standard MHz PECVD from 99 % H diluted SiH 4 yields high purity and high crystallinity nc-si:h thin films. Ambipolar TFTs made of nc-si:h show n-channel mobility about 150 cm V -1 s -1 and p-channel mobility of 30 cm V -1 s -1. Highest reported to-date and first demonstration of PECVD CMOS. Integration approaches presented are very promising for x-ray imaging and displays with extremely high fill factor and resolution, as well as for system-on-panel integration!