Atomic Level Material and Device Analysis for FinFET and Nanowire Design

Transcription

1 Atomic Level Material and Device Analysis for FinFET and Nanowire Design Victor Moroz, Søren Smidstrup, Munkang Choi, and Alexei Svizhenko July 13, Junction Technologies User Group Meeting 2018 Synopsys, Inc. 1

2 Number of atoms How Many Atoms Are We Talking About? 100,000,000 10,000,000 1,000, ,000 Atoms in transistor Atoms in channel Trend ,990, ,480 11,089,920 28,200,960 30x 364, ,400 Number of atoms per transistor is reducing by ~30% per generation At that pace, transistor can be scaled for another couple of decades before approaching variability & leakage limits 10,000 Variability + Leakage Scaling limit Technology node, nm 2018 Synopsys, Inc. 2

3 Definition of Ab initio Modeling Approach 2018 Synopsys, Inc. 3

4 Ab initio Analysis Approaches vs Structure Size PDEs & ODEs Atomistic Ab initio SPICE TCAD Force Field Tight Binding LCAO Plane-wave Plane-wave with Hybrid Functional Plane-wave with GW Practical maximum structure size Complexity Logic block Transistor & small cell ~1,000,00 0 atoms ~100,000 atoms ~10,000 atoms ~300 atoms ~100 atoms ~20 atoms Modeling demand Realm of periodic structures Circuit Whole transistor Piece of transistor Bulk Ref. Structure size 2018 Synopsys, Inc. 4

5 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 5

6 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 6

7 Pattern Collapse Mechanisms Capillary forces at wet cleaning Push-pull during STI densification Thermal mismatch stress Zipping effect during deposition 2018 Synopsys, Inc. 7

8 Pattern Bending Due to Zipping Effect Layer deposition over a patterned structure 2018 Synopsys, Inc. 8

9 Pattern Bending Due to Zipping Effect Let s zoom into the interesting part and look at it on atomistic scale 2018 Synopsys, Inc. 9

10 Pattern Bending Due to Zipping Effect Atomistic amorphous oxide Full scale structure 2018 Synopsys, Inc. 10

11 Molecular Dynamics: Zipping of the 8 o Oxide Gap Timeline: initial 2018 Synopsys, Inc. 11

12 Molecular Dynamics: Zipping of the 8 o Oxide Gap Timeline: initial intermediate 2018 Synopsys, Inc. 12

13 Molecular Dynamics: Zipping of the 8o Oxide Gap Timeline: initial 2018 Synopsys, Inc. 13 intermediate final

14 Molecular Dynamics: Zipping of the 8o Oxide Gap Timeline: initial 2018 Synopsys, Inc. 14 with intermediateinteraction starts final Van der Waals bonds, and eventually switches to covalent bonds

15 Molecular Dynamics: No Zipping of the 10o Oxide Gap Timeline: initial 2018 Synopsys, Inc. 15 intermediate final

16 Molecular Dynamics: No Zipping of the 10o Oxide Gap Timeline: initial intermediateno zipping, just final a few bonds at the bottom of the gap 2018 Synopsys, Inc. 16

17 Interaction of the Oxide Layers vs Gap Width 2018 Synopsys, Inc. 17

18 Interaction of the Oxide Layers vs Gap Width Two attraction peaks at 3.4 Å and at 1.9 Å Sweet spot at 0.8 Å Repulsion below 0.8 Å 2018 Synopsys, Inc. 18

19 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 19

20 Structure size & Modeling speed Predictive power Advanced Electron Transport DFT NEGF T.B. NEGF K.P. NEGF Effective mass NEGF Sub band Boltzmann Full band Boltzmann Requires calibration to advanced transport Drift-Diffusion 2018 Synopsys, Inc. 20

21 Ballistic Ratio Quasi-Ballistic Electron Transport Scaling timeline Ballistic ratio keeps improving with scaling And projected to improve towards 2nm design rules for FinFET or nano-slab One important side effect is that fundamental physics plays increasing role, and there s less need for calibration Channel Length, nm 2018 Synopsys, Inc. 21

22 physics Ballistic Ratio Mobility calibration Quasi-Ballistic Electron Transport Scaling timeline 0.8 Ballistic ratio keeps improving with scaling 0.6 And projected to improve towards 2nm design rules for FinFET or nano-slab One important side effect is that fundamental physics plays increasing role, and there s less need for calibration Channel Length, nm 2018 Synopsys, Inc. 22

23 Ballistic Ratio Fundamental physics physics Mobility calibration calibration Quasi-Ballistic Electron Transport Scaling timeline 0.8 Ballistic ratio keeps improving with scaling 0.6 And projected to improve towards 2nm design rules for FinFET or nano-slab One important side effect is that fundamental physics plays increasing role, and there s less need for calibration Channel Length, nm 2018 Synopsys, Inc. 23

24 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 24

25 Modeling S/D Contact Resistance (G. Pourtois, IMEC) Fundamentals Today: ~1e21 e /cm 3 2x10-9. cm 2 Can we reach cm 2? Is there a theoretical limit to it? [1] A few practical difficulties: TiSi x crystallites in a-tisi alloy [2] [2] B no PAI C 600ºC A 3keV [1] Yang, JAP 98, , 2005 [2] H. Yu et al, IEDM Amorphous & polycrystalline interfaces How do we model this? Atomistic simulations 2018 Synopsys, Inc. 25

26 How to Get Amorphous Material? (G. Pourtois, IMEC) Initial: crystal melt & quench process Final: amorphous Crystal TiSi 10% relaxed crystal Melted TiSi 10% melt shrink Quenching 2018 Synopsys, Inc. 26

27 System Size & Interface Models (G. Pourtois, IMEC) Si body 5 nm a-tisi 4nm Si Left electrode Interfacial region ~7.8 nm Right electrode Methodology: The Si body should be at least 4 nm e /cm 3 To account for a proper depletion length o DFT & NEGF: o TB functional (c=1.08) band gap Si: 1.18, Ge: 0.66 ev o Lattice mismatch < 1% - tailored amorphous model o Uniform doping o 260 atoms model o SZP basis 2018 Synopsys, Inc. 27 Slide 27

28 Probing different interface topologies Interface Models (G. Pourtois, IMEC) Model 1 Si Ti Model 2 different interface configurations Model 3 Model 4 Avatar (movie 2009) resources: CPU Resources used for this project: o 34 racks, each 4 chassis, 32 machines each o 40,000 processors, 104 terabytes of memory o 4 cores processors 160,000 cores o Run time: ~ 3 hours, i.e. 480,000 core-hours o o Total CPU usage so far: 453,120 core-hours Similar to Avatar movie 2018 Synopsys, Inc. 28

29 Contact resistance (Ohm.cm2) n-si[100] a-tisi (G. Pourtois, IMEC) Doping: n-1xe 20 e /cm 3 Doping: n-3xe 21 e /cm 3 1.E E-08 empty empty Experiment [1] E F occupied >0 E F occupied <0 1.E E-09 Distorted Si & MIGS What do we learn? 1.E E E E-10 Si a-tisi Si a-tisi o cm 2 is possible with high doping and by matching metal/semi effective carrier masses o Good agreement with Si data 3e21 P 1.E E-10 1.E+20 1.E+21 1.E+22 Doping concentration [1] Yu et al, IEEE TEL Devices, Vol. 63 (12), Synopsys, Inc. 29

30 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 30

31 2018 Synopsys, Inc. 31 S. Hung at IEDM 2017 short course

32 Hi-K Metal Gate: Vt Tuning, Traps, Variability gates One transistor contains millions of atoms, too much for atomistic models to handle fins So, we split it into several samples where we can apply atomistic analysis One transistor Intel s 22nm FinFETs, SEM by DFT Bandstructure samples FinFET top view Metal fill WF metal HK IL oxide Fin channel S/D extension S/D epi SiON spacer 2018 Synopsys, Inc. 32

33 M2 M3 D1 SiO2 Atomistic Analysis of the Multi-Layer Gate Stack HKMG: Many layers of metals and dielectrics Complicated bandstructure Surface roughness Tunneling Traps Goal: predict and engineer device behavior such as Vt tuning, variability, traps, electron transport, leakage W M1 Si SiO2 D1 M3 M2 M1 W HKMG: stack of thin layers 2018 Synopsys, Inc. 33

34 HKMG Modeling approach Molecular dynamics: empirical pseudopotentials or DFT Melt-and-quench to obtain amorphous materials Optimization of interface atomic configurations Atomic positions are used as an input for electronic calculations Melting and quenching of SiO2 Electronic calculations: DFT-NEGF Band structure in the fin Work function, barriers, local DOS across the stack Tunneling through the stack Extract essential properties for transistor scale analysis 2018 Synopsys, Inc. 34

35 Case study: W/aTiN/aHfO2/aSiO2/Si/aSiO2/aHfO2/aTiN/W DOS Hartree potential 2018 Synopsys, Inc. 35

36 Atomistic Analysis of NCFET (Pawel Lenarczyk, ETH, Zurich) non-polar: P = 0 Material behavior Device behavior c polarized: P = 0.22Cm 2 a spontaneous polarization [cm 2 ] calculated 0.25 experimental Synopsys, Inc. 36

37 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 37

38 Si Stacking Fault DFT Analysis (A.Pourghaderi, Samsung) Type B Type C Side view Green color for is for guiding the eyes only (not dangling bonds) Side view 2018 Synopsys, Inc. 38

39 IDS (a.u) Si Stacking Fault DFT Analysis (A.Pourghaderi, Samsung) Type C d c Shape of wavefunctions Localized near the crossing point of stacking faults 1.0E E E E E-03 Pristine TypeB TypeC TypeB results match the leakage level & floor in HW b a b 1.0E VGS (V) a Green: pristine silicon bandstructure Red: bandstructure of Si with crossing stacking fault c d Bulk-like wavefunction (inside cond. band) DFT calculation details Quantumwise GGA-PBE exfunctional SingleZeta basis function (minimal) (in relaxation calculation) Force criterion: 0.05eV/A Number of atoms in each structure: Type B and type C: 2,808 (4 unitcell thick in z direction) TAT: Relaxation within 3~5 days using 144 cpu cores 2018 Synopsys, Inc. 39

40 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 40

41 Plasma Etch Damage Analysis: Fluorine Hitting Silicon Timeline: initial Bombarding Si by F + ions 2018 Synopsys, Inc. 41

42 Plasma Etch Damage Analysis: Fluorine Hitting Silicon Timeline: initial intermediate Bombarding Si by F + ions Molecular dynamics analysis of accumulating damage 2018 Synopsys, Inc. 42

43 Plasma Etch Damage Analysis: Fluorine Hitting Silicon Timeline: initial intermediate final Bombarding Si by F + ions Molecular dynamics analysis of accumulating damage Several nm of Si are damaged and contaminated Early stages 2018 Synopsys, Inc. 43

44 Surface roughness Channel material Extended defects Interconnects: barriers, EM Collapse of fins and pillars NEGF: DFT, TB, K.P, EMA Carrier transport thru dielectrics Plasma etch damage in low-k & Si HKMG: Vt, band structure, Dopant diffusion and Ferroelectrics and NCFET activation Dopant diff. and activation in bulk material Dopant diff. and activation in thin layers Chemical reactions in Epi, ALD, ALE Contact resistance: MIS, silicide, melt Outline Emerging memory: ReRAM, PCM, OTS, Ab-initio analysis Process flow Design rules BSIM Parasitic RC TCAD Manufacturing & Design 2018 Synopsys, Inc. 44

45 Summary Increasing number of technology issues require understanding on atomic level to enable material engineering and transistor design Thin layers (below ~5nm) exhibit different properties than bulk material and can only be accurately analyzed by atomic methods We reviewed application of ab initio analysis tools to characterize some of the major technology issues 2018 Synopsys, Inc. 45