Impact of the source/drain implants on threshold voltage matching in deep submicron CMOS technologies

Transcription

1 Impact of the source/drain implants on threshold voltage matching in deep submicron CMOS technologies Jerôme Dubois 1, Johan Knol 1, Hans Tuinhout 2, Jurriaan Schmitz 2, Peter Stolk 2 and Mike Bolt 1 1 Philips Semiconductors, MOS4YOU, Nijmegen, The Netherlands 2 Philips Research, Eindhoven, The Netherlands

2 Introduction: Matching Threshold voltage matching describes the fluctuation of the threshold voltage between identical closely located transistor pairs. Threshold voltage matching is affected by the gate oxide thickness and the channel dope fluctuations σ( V t ) = A vt (WL) -1/2 σ( Vt) [mv] / (area) [1/µm] Semiconductors 2

3 Introduction: Description of the problem σ( Vt) [mv] NMOS A vt as a function of process generation: A vt ~ T ox process generation [µm] σ( V t ) of the NMOS for the minimum area transistor as a function of process generation: σ( V t )=A vt (W min L min ) -1/2 1.0 Semiconductors 3 Avt [mvum] Tox [nm]

4 Short process overview 1) Situation after poly etch α-si STI Substrate Semiconductors 4

5 Short process overview 2) Situation after poly oxidation poly-si Semiconductors 5

6 Short process overview 3) Situation after NLDD implantation As LDD implant Semiconductors 6

7 Short process overview 4) Situation after spacer formation Semiconductors 7

8 Short process overview 5) Situation after HDD implant As HDD implant Semiconductors 8

9 Experiments: Influence of LDD & HDD implant energy Avt (mvµm) HDD implant As at 40 kev 6.5 HDD implant As at 60 kev LDD implant energy (kev) A reduction of the implant energy of both LDD and HDD improves the threshold voltage matching Tails of the LDD and HDD implants partially channel through the gate poly into the channel area, thus causing additional fluctuations of the channel dope Semiconductors 9

10 Experiments: Influence of the poly thickness Increasing the poly thickness improves the threshold voltage matching behavior Channeling tails can be reduced by increasing poly thickness NMOST Avt (mvµm) Poly Thickness (nm) Semiconductors 10

11 Experiments: Influence of the poly reoxidation thickness Poly reoxidation oxide serves as a scatter oxide for the LDD implants Poly reoxidation oxide reduces channeling in poly gate layer NMOST Avt (mvµm) Poly Re-Oxidation (nm) Semiconductors 11

12 Experiments: Influence of the poly morphology The poly morphology as deposited can change matching performance dramatically α-si Poly-Si A Vt (mvµm) Fine grained poly reduces the LDD and HDD channeling tails through the gate poly into the channel area Semiconductors 12

13 Experiments: Influence of pocket implant energy Avt (mv µm) SD impl As 10 kev Experiments in a nonoptimized 0.18 µm process show that pocket implant energy is also important for matching Pocket implant also has channeling tails into the channel area pocket impl. energy (kev) Semiconductors 13

14 Summary Reduction of the implant energy to reduce channeling channeling increased oxide layer to reduce channeling Fine grained poly to reduce channeling Semiconductors 14

15 Conclusions A new mechanism responsible for degeneration of the threshold voltage matching performance of deep sub-micron CMOS technologies has been identified. Due to the reduction of the poly gate thickness for advanced technologies, (random) penetration of a small fraction of the LDD and HDD implants into the channel area may occur. This severely deteriorates matching behaviour. The extent of this effect depends on the implant energies, gate thickness, poly re-oxidation layer and poly gate morphology. Due to the reduction of the gate layer thickness and introduction of more elaborate device architectures for advanced deep sub-micron technologies (e.g. Halo's or pockets), careful evaluation and control of threshold voltage fluctuation enhancement effects like the phenomena discussed in this paper, form indispensable elements of CMOS device architecture optimisation. Semiconductors 15

16