MOS interface processing and properties utilizing Ba-interface layers

Transcription

1 MOS interface processing and properties utilizing Ba-interface layers Daniel J. Lichtenwalner, Vipindas Pala, Brett Hull, Scott Allen, & John W. Palmour Power R&D, Cree, Inc. Durham, NC Partial funding from the Army Research Laboratory, Adelphi, MD 2015 ARL-workshop, University of Maryland August 13, 2015

2 OUTLINE 1. Motivation 1. Channel resistance 2. MOS interface passivation 2. Experimental: interface modification 3. MOSFET channel properties 1. Field-Effect Mobility & interface charge 2. DMOS R DS(on), switching 4. MOSFET gate oxide properties 1. Electrical properties 2. Material characterization 5. Summary 2

3 Ron,sp (mohm-cm 2 ) 1.1 Motivation: Channel resistance Cree Gen3 1200V devices projected to have R on,sp ~2.7 mohm-cm 2 With current NO process (FE mob~18), R CH ~1 mohm-cm 2 Doubling the channel mobility would reduce R on,sp by ~16% V Gen3 Hi-mob benefit 2.7 mohm-cm mohm-cm 2 MOS chan 0.95 MOS chan 0.45 Ohmic Ohmic Driftrelated Driftrelated Subs Gen3 Subs hi-mob Gen3 3

4 1.2 MOS interface passivation approaches The Ideal Passivation: Concentration N IT (~10 13 cm -2 ) All at the interface Thermally stable GROUP I elements: H, Na: interface passivation, & interface sheet charge; but mobile General trend: (demonstrated by Na) Un-passivated thermal oxide: mobility~0 D IT passivation ~smooth mobility curve Counter-doping (or sheet charge) ~peaked mobility curve, lower V T Tuttle et al., JAP 109 (2011) GROUP V elements: N, P, As, Sb: mix of interface passivation & counter-doping Other elements: Group II: Sr, Ba (Cree) Group III: La (V. Misra group, NCSU) lowering of D IT observed See: Liu, Tuttle, Dhar, Appl. Phys. Rev. 2, (2015) 4

5 2. Experimental: Si-face, 4H-SiC MOSFETs Lateral & Vertical MOSFETs: Al-doped p-type SiC (0001) channel Thin evaporated Ba (or Sr) passivation layer Deposited SiO 2 gate oxide Oxide annealed in O 2 /N 2 Poly-Si gate (B-doped) Ni ohmic IL S Gate SiO 2 P-epi SiC D N+ N+ Electrical Measurements: I D -V D I D -V g vs Temp (V T, F.E. mobility) Quasi-static gate C-V (T ox, V fb, V T, Q f ) Gate I g -V g (CB, VB F-N barrier height, E BD ) Materials Analysis: Spectroscopic Ellipsometry SIMS AFM 5

6 Mobility (cm 2 /V. s) Current (A) Mobility (cm 2 /Vs) 3.1 MOSFET Field Effect mobility Significant Mobility enhancement with alkaline earth elements Sr and Ba. 5E15 p-doping level Id-Vg for lateral MOSFET with Babased interface layer: Low gate leakage V T ~1.2 V Ba IL Sr IL 'NO' no IL Ca IL Gate Voltage (V) E E E E E-08-8 I D 1.0E E E-11 I G E E E mobility Gate Voltage (V)

7 Mobility (cm 2 /V. s) Mobility (cm 2 /V. s) 3.1 MOSFET F.E. mobility: Temperature & doping Ba-IL vs NO, 5E15 doping: NO-anneal: coulomb scattering effects (high D IT near CB) Ba IL: phonon scattering dominates (low D IT near CB) 'NO' 150 o C 25 o C Ba IL 25 o C 100 o C 150 o C Gate Voltage (V) Peak mobility vs doping: Mobility decreases with doping; as expected mobility with Ba-IL remains above the value with NO anneal Ba IL 'NO' 0 1E+15 1E+16 1E+17 1E+18 1E Doping (atoms/cm 3 ) 7

8 D IT (cm -2 ev -1 ) 3.1 MOS interface charge (C-V of n-cap)* D IT & Q f from fit to C-V: N IT = (-) cm -2 Q f(eff) = (+) cm -2 D IT : thermal vs NO anneal vs Ba IL Ba IL clearly provides D IT reduction, slightly better than NO process. 1E E thermal oxide thermal+no Ba IL 101E E E E - E VB (ev) E F E c *underestimates true D IT ; see A. V. Penumatcha, S. Swandono, & J. A. Cooper, IEEE TED 60, (2013). 8

9 R on,sp (mw-cm 2 ) V 15A DMOS R on,sp 1200V DMOS: High-mob vs NO control 1200V DMOS: High-mob BEST 15A Gen3 DMOS with high-mobility Ba IL provides ~0.5 mw-cm 2 reduction in R ON,SP Gate Voltage (V) Low R ON,SP with V G below 20V 9

10 Vds(V) Ids (A) Energy (uj) V 15A DMOS: packaged device switching High-mob switching: 800V D, 15A V G -5 to +20V, T J = 25 C R G(ext) = 6.8 Ω, L = 856 μh Packaged 1200V 15A Hi-mob device 1,200 1, Vds Ids -1E-06-6E-07-2E-07 2E-07 6E-07 1E-06 Time (s) Packaged devices compared: Gen3: Control vs Hi-mob Switching loss - 800Vd, -5/+20Vg Hi-mob Control E total E on E off Drain Current (A) High-mobility oxide process does not adversely affect switching loss 10

11 4. MOSFET gate oxide properties 11

12 4.1 MOS gate oxide: effective FN barrier height Ideal SiO 2 on SiC: J. Robertson, B. Falabretti, Mat. Sci. & Eng. B 135, 267 (2006). CB barrier: NO: 2.84eV Ba IL: 2.80eV Measured Oxide I-V: VB barrier: NO: 3.05eV Ba IL: 2.79eV FN plot: slope (B) = 6.83E7*(m ox /m) 1/2 *PhiB 3/2 m ox (e)=0.42*m; m ox (h)=0.58*m (Chanana, APL (2011)). FN Barrier heights ~good with Ba-IL; but VB offset lower. 12

13 Drain Current (A) Drain Current (A) 4.1 High-mobility: 1200V DMOSFET blocking Many devices block to the avalanche limit of the drift layer Some devices have early blocking failure 1E V 15A hi-mob DMOS blocking 1E V 15A hi-mob DMOS blocking 8E-06 6E-06 ~1650V 8E-06 6E-06 4E-06 4E-06 ~1200V 2E-06 2E-06 0E ,000 1,500 2,000 Drain Voltage (V) 0E ,000 1,500 Drain Voltage (V) Blocking failures mainly due to gate oxide breakdown The high-mobility process requires optimization 13

14 4.1 MOS gate oxide: Breakdown Field Ramped V G large n-caps (2x2 mm 2 ) Qty>100 High-mob oxide: ~15% lower E BD High-mob oxide: more extrinsic failures control thermal oxide+no Highmobility oxide Need for continued study to improve oxide reliability 14

15 Current (A) Current (A) V T (V) 4.1 High-mobility: NBTI / PBTI V T stability High-mobility 1200V packaged devices: 150C, -15V G & +15V G stress, 100hrs No NBTI V T shift some PBTI V T shift 1E+00 1E-03 1E-06 1E-09 1E-12 Pkgd hi-mob DMOS NBTI -15V 150C CJ06W3 # t=100hr t= Gate Voltage (V) 1E+00 1E-03 1E-06 1E-09 1E-12 Pkgd hi-mob DMOS PBTI 15V 150C CJ06W3 # t= 0 t=100hr Gate Voltage (V) o C: NBTI -15V g, PBTI +15V g PBTI DV T ~1V NBTI DV T <0.1V stress time (hr) High-mobility oxide process may introduce some positive threshold shift; further study needed 15

16 SiO 2 growth (nm) 4.2 Materials characterization: oxidation (ellipsometry) Ba & Sr IL enhances oxidation rates of both Si and SiC Can be fit with Deal-Grove model, with appropriate parabolic and linear rate constants The Ba (and Sr) greatly increase the linear rate constant, consistent with an increased interface reaction rate Deal-Grove Paralinear oxidation rate model: X ox +A*X ox = B*(t+t) Where: B = parabolic rate constant (diffusion-limited) C anneal, 20% O 2 Si: Ba IL Si: no IL SiC: Ba IL SiC: Sr IL B/A = linear rate constant (interface-reaction-limited) Lines: Deal-Grove fits (JAP 36, 3770 (1965)) 0 SiC: no IL PDA time (min) 16

17 Conc (cm -3 ) Conc (cm -3 ) 4.2 Materials characterization: Ba depth profile (SIMS) 30nm SiO 2 /Ba IL/SiC: as-fabricated VS after enhanced oxidation Approximate Ba concentration, as sensitivity factor in SiO 2 & SiC uncertain 10 1E+24 1E E+22 1E E+20 1E E E E E E ºC 1hr O 2 /N 2 anneal 950 ºC 10hr O 2 /N 2 anneal dep SiO 2 SiC 900 o C 1hr 20% O 2 anneal Depth (μm) 16 O 28 Si 12 C 138 Ba 10 1E+24 1E E+22 1E E+20 1E E E E dep MEO SiO 2 SiO 2 SiC 1E o C 10hr 20% O 2 anneal 10 1E Depth (μm) 16 O 28 Si 12 C 138 Ba Ba is concentrated/stays mainly at the interface, <30ppm in the oxide 17

18 4.2 Materials characterization: oxide morphology (AFM) AFM images of SiC after gate oxidation reveal: SiC step-bunching in some samples 20x20 um C, 2hrs, RMS 1.75 nm SiO 2 crystallites Size = f(temp) 20x20 um C, 1.7hr, RMS 1.75 nm Either could affect oxide breakdown 18

19 5. Summary Alkaline earth elements Sr and Ba are effective for Si-face SiC mobility enhancement Ba IL provides D IT values slightly lower than that of NO anneals V T is stable under NBTI stress; while electron trapping occurs with PBTI (no mobile ions) FN tunneling shows that the CB offset is unchanged, while the VB offset is slightly reduced, with Ba at the interface SiO 2 oxide breakdown strength is reduced with Ba from ~11.5 MV/cm to ~10 MV/cm, with more extrinsic failures indicating oxide defects Optimizing the oxide strength and oxide reliability are keys for this or other passivation approaches supplanting the NO anneal process 19