Heat Dissipation Capability of a Package-on- Package Embedded Wafer-Level Package

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1 1 Heat Dissipation Capability of a Package-on- Package Embedded Wafer-Level Package Yong Han, Boon Long Lau, Boo Yang Jung, Xiaowu Zhang, Senior Member, IEEE Abstract As the embedded wafer-level packaging technology evolves to capitalize on package-on-package (POP) technology, thermal analysis has been performed to investigate and improve the heat dissipation capability of the 3D package. The simulation scheme is validated with available experimental results. The thermal impacts of internal factors (properties and geometries) are studied and compared. Without increasing the POP footprint size, the thermal cap provides additional thermal paths for heat conduction enhancement, and enables high temperature reduce. Of larger size and direct thermal path to PCB, the package lid achieves enhanced heat conduction and convection, and enables higher heat dissipation capability of the POP. With the developed passive cooling solutions, a total heating power of 4W (top 1W, bottom 3W) can be dissipated, while maintaining the maximum die temperature under operation limit. Index Terms Thermal management, 3D package, Fan-out embedded wafer level package, heat spreading capability. T I. INTRODUCTION HE embedded wafer-level packaging (ewlp) is an enabling technology for miniaturized, fine pitch, high density 3D and advanced silicon packaging solutions [1]. The ewlp leverages on fan-out redistribution connections, streamlining the packaging process [2,3]. The ewlp evolves to capitalize on the package-on-package (POP) technology, which can achieve product miniaturization by package stacking for the mobile and handheld applications [4]. The highly compact size will result in heat dissipation challenges. The thermal crosstalk between the packages in vertical direction makes this challenge more severe. Effective thermal management is essential for best performances of 3D package. Several theoretical and experimental studies have been conducted to estimate the heat dissipation of the POP structure. Bower conducted the simulations and experiments to study the properties impact on the thermal performance of the POP type devices [5]. The maximum heat loaded in the package is 1.5W (0.2W top, 1.3W bottom). Nagendrappa analyzed the effect of the thermal via, solder ball and die size on the thermal resistance of the Fan-in POP [6]. The package. The heat is loaded either on top die or bottom die in their study. Several simulations have been performed by Hoe to analyze the thermal performance of the EMWLP POP with two dies [7]. The inter heat slug and top heat spreader were employed, and less than 3W power can be dissipated while maintaining the maximum die temperature under 85 C. Qiu conducted the FEM analysis of POP heat dissipation [8]. The effects of the logic and memory die power, and the thermal conductivities of PCB and substrate were studied. The maximum logic die power considered in their work was 1.5W. In this work, the thermal analysis is performed to investigate and improve the heat dissipation capability of the fan-out ewlp POP structure. The simulation scheme was validated with the available experimental results conducted previously by Hoe [9]. The 3D package studied is shown in Fig.1. The thermal performance of the initial POP structure is evaluated as the baseline case. Then, the impact of the internal factors (thermal properties and geometries) on heat dissipation capability of the 3D packages is investigated and compared. In the mobile device scenario, passive cooling solutions are explored for heat removal improvement. The topside thermal cap provides additional thermal paths between the top and bottom package, and achieves pronounced temperature decrease. The package lid of larger size and direct thermal path to PCB has enhanced the heat spreading capability, and achieved effective heat conduction from both top and bottom packages to the outside environment. A total heating power of 4W in the POP can be dissipated, while maintaining the maximum die temperature under the operation limit (85ºC). This work is the results of a project initiated by the 12th IME Electronic Packaging Research Consortium (EPRC), the members of which are Ajinomoto, EV Group, Tokyo Ohka Kogyo, Academy of Public Security Technology (Hefei). The authors are with Institute of Microelectronics, A*STAR, Singapore. Direct questions and comments about this article to Yong Han, Institute of Microelectronics, A*STAR, Singapore hany@ime.a-star.edu.sg Fig.1. POP embedded wafer level package structure and the connection layouts of the two packages

2 2 II. CONFIGURATION AND SIMULATION MODEL The computational fluid dynamics (CFD) software, ANSYS ICEPAK is used for package-level thermal management of the current POP structures. Based on ANSYS FLUENT solver, it combines advanced solver technology with robust meshing options. Thermal characteristics of the package under natural convection are evaluated, where the model is built following JEDEC 51-2 Standard [10]. The solution was tested for mesh independency by refining the mesh size. Temperature matched within 1% for both mesh sizes. 3D double-precision pressure based solver is selected. Standard discretization scheme is used for the pressure equation, while second order discretization scheme is adopted for both momentum and energy equations. Instead of modeling the package in full detail for the solder/underfill, RDL layer and TMV/mold part, cuboids with equivalent thermal conductivity are adopted for simplification. The equivalent thermal conductivities in the inplane and through-plane direction are calculated based on volume averaging method [11]. The models are built in a natural convection environment of opening boundaries. For validation of the scheme, the thermal performance of a ewlp package with single die is investigated, and compared with the available experimental results [9]. The package has a 10 10mm 2 footprint with a thickness of 0.3mm. The silicon die is of size mm 2 and thickness 0.1mm. A peripheral array of 206 solder balls and one RDL layer are included in this package, as is shown in Fig.2(a)(b). The simulation model is built as is shown in Fig.2(c)(d). The simplified solder layers covering the solder array areas are considered in the model, and the gap space is filled with air. This model consists of around 0.5 million hexahedron elements. The heating power of 0.5~2W was supplied to the chip. As is illustrated in Fig.2(e), great agreement has been obtained between the simulation and experimental results, suggesting that the thermal performance of the ewlp package is accurately simulated. The same simulation scheme is used for the thermal analysis of the POP structure, as is shown in Fig.3(a). The package design has the following specifications: the top package size is 8 8mm2 with a mm 3 memory die; the bottom package size is 14 14mm 2 with a mm 3 logic die; the numbers of I/O are 168 and 736 in the top and bottom package respectively. The fan-out POP structure incorporates 192 Cu-filled through mold vias (TMV) of the 100µm diameter and 400µm pitch in the bottom logic package to provide short electrical connection from the top package to the board level. The package has depopulated solder arrays, consisting of 168 SnAg solder balls of 300μm diameter and 0.5mm pitch under the top package, and 736 SnAg solder balls of 250μm diameter and 0.3mm pitch under the bottom package. There are 3 RDL layers in the POP, and the Cu percentage in each layer is around10.3%. In the simulation, the thermal conductivity (k T ) of the silicon chip is 138W/mK, the solder ball is 78W/mK, and the PCB is 0.4W/mK(throughplane) and 18.99W/mK(in-plane) [11]. Fig.2. The ewlp package with single die: (a) Schematic image, (b) connection layout of the test vehicle, (c) cross-section view of the simulation model, (d) top transparent view of the package, and (e) thermal performance comparison. Fig.3. POP simulation model: (a) cross-section image of the whole model Cross-section images of the POP simulation model, (b) top view, (c) mesh distribution, (d) solder layer of bottom package, (e) solder layer of top package, and (f) mold compound of the bottom package

3 3 The mesh independence is established when the total elements are more than 1.5 million in the designed structure. The solder layers of equivalent thermal conductivities are considered in the solder-array covering areas, and the inbetween gap is filled with pure underfill material. Similar assumption has been made to the TMV part in the bottom package, as is shown in Fig.3(f). III. THERMAL PERFORMANCE INVESTIGATION To evaluate the thermal performance of the original structure as described above, total power of 2W was applied (Bottom die: 1.5W and top die: 0.5W). As the baseline case, the results are illustrated in Fig.4(a). The ambient temperature is 25ºC.The maximum temperature of the whole package, which happens at the top die, is 88.66ºC. The maximum temperature of the bottom die is about 2ºC lower than the top die for the 2W power heating. Several simulations have been conducted by supplying different dissipation power to the packages. In the baseline case, to dissipate a total power of 2W, the maximum temperature already reaches as high as 85ºC. Subsequently, the impact of internal factors (thermal properties and geometries) on the thermal performance of the POP are investigated and compared for 2W power heating. The solder layer in baseline case is with 0.9W/mK underfill. In contrast with the no-underfill solder layer, this withunderfill layer enabled around 1ºC max temperature decrease for the POP structure with 2W power. By increasing the thermal conductivity of the underfill layer, the in-plane heat conduction can be highly enhanced, which will enable better heat spreading capability for the solder layer. Compared with the baseline case, the maximum temperature can be reduced by 2.41ºC with underfill of 5W/mK, and the cooling effects are similar for both packages. The effect of increasing the thermal conductivity of the mold compound was explored based on the range from 0.8W/mK to 5W/mK. The thicknesses of the mold in both top and bottom package are 300µm, which means 100µm overmold thickness. The junction temperature achieved up to 5.4% cooling for the top die, and 4.1% cooling for the bottom die, when the thermal conductivity of the mold is increased from 0.8 to 5 W/mK. With mold of 5W/mK, the temperature difference between top and bottom die could be reduced to about 0.5ºC, suggesting smaller thermal resistance had been enabled by enhancing the heat conduction of the mold. Another parameter of the mold compound that the design can evaluate is the thickness of the overmold. The combination effects of the thermal conductivity and overmold thickness are shown in Fig.4(b). With mold compound of lower thermal conductivity (0.8W/mK), the overmold part resulted in larger thermal resistance as the heat transfer block, and thinner one can achieve about 1% cooling for the top die and negligible effect for the bottom die. With mold compound of higher thermal conductivity (3W/mK), the overmold part could enhance the heat spreading for the heated dies, and the thickness effect on thermal performance is quite weak. Thinner overmold, enabling reduced thermal resistance, could enhance the crosstalk effect between both packages. Fig.4. Thermal performance of the POP with 2W power heating: (a) temperature distribution of the baseline case, (b) overmold effect, and (c) Cu percentage effect There are three RDL layers in the POP for the high number of I/Os, as is shown in Fig.4(c). For inside package heat conduction improvement, increasing the Cu percentage will be an effective method. Compared with the baseline case of 10.3% Cu content, the 50% Cu content can increase the inplane thermal conductivity by up to 3.75 times, suggesting highly improved heat spreading capability of the RDL layer. The maximum temperature of the top and bottom die will drop 5ºC, when the Cu percentage increases from 10.3% to 50%. In baseline case, the polyimide (k T =0.52W/mK) passivation layer is used. By using passivation materials of higher thermal conductivities, Al 2 O 3 (30W/mK) or AlN (180W/mK), better heat conduction capability can be obtained. The thermal effects of the passivation materials are listed in Table I, compared with the other affecting factors.

4 4 Table I THERMAL EFFECT COMPARISON OF INTERNAL FACTORS Cases Underfill thermal conductivity (W/mK) Overmold Thickness (µm) k T (W/mK) k T of passivation RDL (W/mK) Cu percentage 10.3% 10.3% 50% 10.3% 10.3% Maximum temperature decrease Top die 2.7% 4.3% 5.7% 4.0% 7.5% Bottom die 2.4% 3.4% 5.3% 3.4% 6.6% (The changed factors are highlighted with underline. The temperature decrease is compared with the baseline case) respectively. The larger heat spreader width has greater cooling impact on the top die, which enables lower top die temperature than the bottom. Based on the above thermal analyses, the internal factors have greater cooling impact on the top die than the bottom die. The main heat dissipation path is through the bottom PCB to the outside environment. In the following section, the passive cooling solutions are employed for enhancement of the topside heat conduction and natural convection. IV. TOPSIDE COOLING SOLUTIONS The Cu top cap of the same size as the bottom package (14 14mm 2 ) is attached on topside of the POP, as is shown in Fig.5(a). The thermal conductivity of the Cu is 387.6W/mK. The sidewall thickness is 1mm, and the top plate thickness is 0.5mm. The thermal interface material (TIM) of thickness 100µm is considered at the contact interfaces between the cap and the packages. The thermal conductivity of the TIM is 1.2WmK. With no internal factor optimization, the top cap enabled 14.7% and 11.8% maximum die temperature decrease for the top and bottom package respectively. The additional thermal paths through the sidewalls can enable enhanced heat conduction form the top package to the bottom package, and from the bottom package to the topside environment. The heat from the top die can be effectively spread to a relatively larger area for heat convection. Lower top die temperature than the bottom was achieved. For 2W heating, the maximum bottom die temperature is 1ºC higher than the top die. Further improvement is achieved by increasing the sidewall thickness as is illustrated in Fig.5(c). Around 2% top die temperature decrease can be obtained by increasing the thickness from 1mm to 2.5mm. The cooling effect is a little more pronounced on the top die than the bottom die. Therefore, the temperature difference becomes a little larger between these two dies. Similar maximum die temperature can be obtained in both packages when the thickness is reduced to zero. In that case, the top cap becomes a normal heat spreader. Without additional thermal paths, the maximum die temperature is 83.58ºC, which is only 5.7% cooling. The thick sidewall of the top cap dominates the cooling effect by providing additional thermal paths for heat conduction enhancement. Doubling the width of the heat spreader, for 2W power, the temperature of top and bottom die can drop up to 11.8% and 10.5%, Fig.5. POP structure with Cu top cap: (a) cross-section image of the simulation model, (b) temperature distribution with 2W power, and (c) thermal effect of the cap sidewall thickness. Of larger size and direct thermal path to PCB, the package lid is adopted for heat dissipation improvement of POP, as is illustrated in Fig.6(a) The lid width is 20mm, sidewall thickness is 2.5mm, the inner wall thickness is 2.5mm, and top plate thickness 0.5mm. The same TIM is considered in this model with package lid. The simulation results in Fig.6(c) show that, to dissipate 2W power, the maximum die temperature of the POP is 65.79ºC, which occurs at the bottom die. Compared with heat spreader cooling, the sidewall and inner wall enable 16.8% maximum die temperature decrease for the 3D package. Besides the enhanced heat spreading, the direct thermal paths enabled improved heat dissipation from the top package to the PCB, and from the bottom package to the topside environment, which allows the whole package to dissipate more heating power as is illustrated in Fig.6. The 85ºC temperature limit can be met, at a total dissipation power of 3W (Bottom: 2W and top: 1W). Similar peak temperature has been achieved for both dies.

5 5 investigate and improve the thermal performance of the Fan- Out POP with two dies. The effects of internal factors (materials and dimensions) on the thermal performance are investigated. Passive cooling solutions are explored in the mobile device scenario for performance improvement. The top cap and package lid are adopted to enhance the package topside heat conduction and convection. The additional thermal paths provided by the cap and lid can enable better cooling capability. Using the top cap, more than 10% temperature drop can be achieved, without enlarging the footprint size of the POP. The 20mm and 28mm package lid can accommodate 3W and 4W heating power respectively, while maintaining the die temperature under the operation limit. The results and conclusions obtained are expected to aid the 3D package design. Fig.6. POP with package lid: (a) cross-section image of the simulation model, (b) temperature distribution with 2W power, and (c) thermal performance with different power dissipation. To dissipate 4W (1W top +3W bottom) heating power, the package lid of different widths combining the internal factor improvement have been applied and compared, as is listed in Table II. By enlarging the size of the package lid, better thermal performance can be obtained. The maximum die temperature can be reduced by 12.5% by increasing the lid width from 20mm to 28mm. Further cooling improvement can be achieved by using the materials of higher thermal conductivities in the structure with package lid. Table II. THERMAL PERFORMANCE COMPARISON FOR 4W HEATING POWER Maximum temperature Cases Package lid width (mm) Internal factor improvement Top die (ºC) Bottom die (ºC) 1 20 No No k T of passivation 180W/mK k T of passivation 180W/mK; k T of mold 3W/mK REFERENCES [1] W.Y. Seung, J.A. Caparas, Y. Lin, and P.C. Marimuthu, "Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (ewlb- PoP) Technology", IEEE ECTC, pp , [2] V. Kripesh, V.S. Rao, A. Kumar, G. Sharma, C.H. Khong, X. Zhang, Y.M. Khoo, N. Khan, and J.H. Lau, "Design and Development of a Multi-Die Embedded Micro Wafer Level Package." ECTC, pp , [3] G. Sharma, V.S. Rao, A. Kumar, N. Su, Y.Y. Lim, C.H. Khong, S. Lim, V. N. Sekhar, R. Rajoo, V. Kripesh, and J.H. Lau, "Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies", ECTC, pp , [4] A. Geczy, and Z. Illyefalvi- Zitez, Package-on-Package-Review on a Promising Packaging Technology, IEEE ISSE, pp , 2010 [5] M. Bower, Y.J. Lee, B. Joiner, and N. Vijayaragavan, Thermal characterization of Package-on-Package (POP), IEEE SEMI-THERM, pp , [6] N. Nagendrappa, N. Okamoto, and F. Barez, Thermal characterization of Fan-in Package-on-Packages, IEEE SEMI-THERM, pp , [7] G. Hoe, C.S. Choong, V.S. Rao, G. Sharma, X. Zhang, and D. Pinjiala, "Thermal Modeling and Simulation of a Package-on-Package Embedded Micro Wafer Level Package (EMWLP) Structure at the Package and System-level", EPTC, pp , [8] X. Qiu, and J. Wang, Study on Heat Dissipation in Package-On- Package (POP), IEEE EPTC, pp , [9] G. Hoe, G. Tang, G. Sharma, D. Pinjiala, V.S. Rao, M.C. Jong, S. Lim, A. Kumar, S.W. Ho, and X. Zhang, " Thermal Modeling and Characterization of the Embedded Micro Wafer Level Package (EMWLP) at the Package- and System-Level, IEEE EPTC, pp , [10] JEDEC Standard No. 51-2A, Integrated Circuits Thermal Test Method Environmental Conditions, Jan, 2008 [11] X.Q. Xing, Y.J. Lee, T.Y. Tee, X. Zhang, S.Gao, and W.S. Kwon, Thermal Modeling and Characterization of Package with Through- Silicon-Vias (TSV) Interposer, IEEE EPTC, pp , V. CONCLUSIONS Package-level thermal analysis has been performed to

6 6 Yong Han is a Research Scientist with the Institute of Research (A*STAR), Singapore. His current research interests include modeling and thermal analysis, advanced packaging, and cooling solutions. Han has a PhD in Electronic Science and Technology from the Institute of Electronics of Chinese Academy of Sciences (IECAS), Beijing, China. Boon Long Lau is a Research Engineer with the Institute of Research (A*STAR), Singapore. His research interests include microchannel and TSV process integration Lau has a B.S. in Chemical Engineering from National University of Singapore. Boo Yang Jung is a Research Scientist with the Institute of Research (A*STAR), Singapore. His current research interests focus on the advanced package development. Jung has a PhD in Material Science from Hongik University, Seoul, South Korea. Xiaowu Zhang is a Principal Investigator with the Institute of Research (A*STAR), Singapore. His current research interests include computational modeling and stress analysis, advanced integrated circuit (IC) and packaging development, and 3-D IC integration with TSV. Zhang has a PhD in Mechanical Engineering from the Hong Kong University of Science and Technology, Hong Kong. He is a senior member of IEEE.