Flip Chip Applications

Transcription

1 June 12 to 15, 2011 San Diego, CA WSP Wafer Wafer Socket Probe for Flip Chip Applications Brandon Mair Norman Armendariz TTC Test Technology Center

2 Agenda Introduction Probe Tip Effect On Bump WSP FCProbe Probe Attributes Approach Test Plan Data Technology Qualification Production Qualification Key Observations Summary Acknowledgments June 12 to 15, 2011 IEEE SW Test Workshop 2

3 Introduction: WSP- Wafer Socket Probe technology has demonstrated better physical, electrical l performance and COO compared to - conventional vertical probe cards on WLCSP devices as observed on 400 um pitch (250um bump dia.) solder balls. Currently, Canti-bump and technologies are used on the smaller bumped FC-Flip-Chip devices. Objective was to determine if the WSP could be scaled down to Flip-Chip geometries (~150um) and validate if similar attributes would also result on both un-reflowed or reflowed spherical bumps. WLCSP Spherical Ball FLIP CHIP Un reflowed Bump FLIP CHIP Spherical Bump June 12 to 15, 2011 IEEE SW Test Workshop 3

4 vs WSP FC Probe Tip Effect on Bump Flat tips impact the top side of the ball (POR). Ball height <1/3 affects SMT process. CRes not as stable, requiring more force and more cleaning to remove compacted debris and reflow. Four Crown tips self-align and pierce the sides with min. damage and no effect on ball ht. with min. CRes. Valleys between tips allow debris to channel away during probing. June 12 to 15, 2011 IEEE SW Test Workshop 4

5 WSP FC PROBE ATTRIBUTES: Self-Aligning 4-8 pts Bump Damage < No reflow req d. Lifetime estm ~ 3 M TDs Planarization not req d. Single-pin repairable CRes < Cost ~ Deflection > Force / pin < Heads Interchangeable Cleaning < June 12 to 15, 2011 IEEE SW Test Workshop 5

6 Probe Attributes: Alignment / Probe Mark pogo-pins tend to self-align and center on solder bump because of 4-pt fulcrum design. No bump damage is observed at the apex, only four small indents on the sides of the bump. June 12 to 15, 2011 IEEE SW Test Workshop 6

7 Probe Attributes: Reparability In terms of reparability, WSP technology relatively easy to repair because individual pins can be replaced ON- SITE, similar to typical BGA sockets. While probing, one pogo-pin was replaced because melted solder stuck to its tip. The process took less than 15 minutes, and subsequent planarization was not required. Melted solder stuck to tip, Single pin quickly replaced ON-SITE. June 12 to 15, 2011 IEEE SW Test Workshop 7

8 Comparative Evaluation Approach A production device was selected as the test vehicle to perform a head-to-head evaluation between a and probe head based on a copy exact test platform. The device chosen was a high performance device with ~6,000 un-reflowed solder bumps ~120um in diameter and on ~190um pitch centers. The qualification process used to qualify and integrate probe card technologies is structured into 2 phases: 1. Technology Qualification 2. Production Qualification June 12 to 15, 2011 IEEE SW Test Workshop 8

9 Comparative Evaluation Approach Probe Head Probe Head MLC Copy Exact PCB + MLC Assembly vs. WSP- FC June 12 to 15, 2011 IEEE SW Test Workshop 9

10 TEST PLAN: WSP FC vs May 2010 Dec 2010 March May 2011 Dallas Test Floor Test Floor PATH FINDING YES WSP- FC TECH EVAL YES WSP- FC PROD EVAL YES TECHNOLOGY QUALIFICATION Technology Validation PRODUCTION QUALIFICATION Production Worthiness NO RTP Determine Recipe Optimize Recipe Baseline BL DATA BL DATA Baseline was also built to ensure a contingent probe solution available. June 12 to 15, 2011 IEEE SW Test Workshop 10

11 Technology Qualification: Test Flow 152TD TDs / Wafer TOTAL TDs = ~ TDs/ Card 6 Wafers 6 Wafers Reprobed Total: 48hrs TQ performed to determine a stable probe process recipe in order to run a production qualification to obtain sufficient volume data to characterize. AVI AVI Prober # 1 Probe Card Wafer 1-6 PROBE CARD Reprobe Wafer 1-6 ~900 TDs ~900 TDs Input Variables: Probe Head Probe Head PH INTERCHANGEABILITY Wafer to Wafer Output Variables: CRes Yield Planarity Alignment Reprobe Rate Tip Length Test / Wafer Time Bump Damage (AVI) June 12 to 15, 2011 IEEE SW Test Workshop 11

12 Technical Qualification: Cleaning Characterization Cleaning Freq. 50PTds Online Cleaning Cleaning Freq. 50Ptds Median: 15.6 Stdev: 1.0 Baseline Median: 17.0 Stdev: Online Cleaning STEPNUM Count Median StdDev NHK Wentworth On initial wafer probed at start of evaluation, WSP CRes statistical lower than. Cleaning sawtooth pattern is observed on every 50 TDs. Tukey-Kramer 0.05 Root MSE = sqrt(2)q* = June 12 to 15, 2011 IEEE SW Test Workshop 12

13 Technical Qualification: CRes Characterization 6 wafers were probed with, then reprobed with 40. CRes STD data is 35 statistical significantly lower than. 30 showed better performance than in many of fthe major CTF probe attributes. As a result TQ was passed with a stable probe/clean process to then proceed to the Production Qualification Phase Count Median StdDev Baseline Median: 16.1 Stdev: 5.6 Median: 15.4 Stdev: 2.0 EY105 SS Tukey-Kramer 0.05 Root MSE = sqrt(2)q*= June 12 to 15, 2011 IEEE SW Test Workshop 13

14 Production Qualification Production Qualification consisted of 4 lots under EWR Engineering Work Request. A 1 : 1 comparison of vs WSP FC technology was performed on one lot. Probing each wafer in that lot with both technologies. Cleaning interval for WSP FC was optimized to every 50Tds. June 12 to 15, 2011 IEEE SW Test Workshop 14

15 Production Qualification: Test Flow 152TD TDs / Wafer ~20k TDs / Leg TOTAL TDs = ~20k TDs/ Card 100 Wafers 13 days Lots 1-3 Prober1 Probe Card 3 Lots 75 Wfrs Prober 2 Probe Card Lot 1 Reprobe 10 Wfrs ~11250 TDs ~1500 TDs Lot 4 PROBER 1 PROBER 1 ~7500 TDs Probe Card Probe Card Wafers 1-14 Wafers 1-25 Reprobe 1-14 Production Qual Sequence run on 1 fresh lot vs. as follows: PROBER 1 Probe Card Wafers Input Variables: Output Variables: Probe Head CRes Reprobe Rate Probe Head Yield Tip Length (Lifetime) Prober to Prober Planarity Test / Wafer Time Wafer to Wafer Alignment Bump Damage (AVI) Reliability June 12 to 15, 2011 IEEE SW Test Workshop 15

16 Production Qualification: CRes Characterization Scatter Plot Lot 1 Lot 2 Lot 3 Lot 4 STEPNUM In Production Qualification, CRes data is more stable except in yellow lot where increased cleaning interval was explored. The red / blue lot does have overall higher CRes than other lots, but CRes is still lower. June 12 to 15, 2011 IEEE SW Test Workshop 16

17 Production Qualification: CRes Characterization Box Plot Count Median StdDev WSP FC EY105 SS Count Median StdDev Tukey-Kramer 0.05 Root MSE = sqrt(2)q* = CRes StdDev of is statistically significantly lower than CRes of Baseline over the span of Production Qualification. June 12 to 15, 2011 IEEE SW Test Workshop 17

18 Production Qualification: vs WSP FC Comparison Pin Count ~6,000 ~6,000 Pitch (um) ~190 ~190 POT (um) LT+60 LT+60 Clean Freq. 50 PTds 50 PTds Alignment (um) 15um 30um (Self-Aligns) Yield % BASELINE 5.30% Cres Mean Ω BASELINE 1.2Ω Cres STD Ω BASELINE 5.42Ω (gm) 19.2g 5.5g Repairability Depends on damage Single-pin replaceable Bump Damage Flattens top of bump 4 small dimples on side CCC (A) 1.2A 1.4A Min. Pitch (um) 100um 150um Max OT 220um 250um Planarization Required Not Required WSP FC Production Qualification: PASS WSP FC shows better performance than in many of the major CTF probe attributes. Production Qualification of WSP FC was passed and WSP FC recommended to RTP Release to production. June 12 to 15, 2011 IEEE SW Test Workshop 18

19 Key Observations: The probe physics of the or interaction of the crown tips with DUT solder bump better addressed the min CRes required and lower force requirements for high-bump count devices w/ higher CCC required. PCO-probe card operations were simplified: Ease of repair Planarization not required Head exchangeability Improved Yield $$$ IEEE SW Test Workshop 19

20 Summary: technology is a viable alternative to conventional probe solution for flip-chip bumped devices with enhanced performance overall, i.e., Lower force and CRes variability. As a result, TI will begin releasing this technology on production test floors and begin the transition from canti-bump and to as production and test configurations warrant. IEEE SW Test Workshop 20

21 ACKNOWLEDGEMENTS Dallas Test Floor Joey Perry Dana Nichols Alysa Rickman Nayef Saleh James Tong Akira Okuma Makoto Yumino Satoshi Shoji Masahiro Takahashi Osamu Ito Kondo-San June 12 to 15, 2011 IEEE SW Test Workshop 21