DESIGNCON High Speed Signal Path Losses as Related to PCB Laminate Type and Copper Roughness

Transcription

1 DESIGNCON 2013 High Speed Signal Path Losses as Related to PCB Laminate Type and Copper Roughness Lee Ritchey, Speeding Edge John Zasio, Speeding Edge Rich Pangier, Isola Corporation Gerry Partida, MEI Corporation DesignCon 2013 High Speed Effects Page 1

2 SYNOPSIS The goal of the following test efforts was to determine how high-speed signal path losses are affected by the types of PCB laminates used as well as the copper surface roughness of those laminates. A number of test efforts were employed to eliminate the variables associated with constructing PCBs at different facilities and at different times and then the measurements resulting from these efforts were correlated. The results obtained were used to determine how loss is impacted by the effect of using smooth copper vs. standard copper. In addition, the lowest cost method for controlling skew was determined and the loss tangent of several materials was established so that this information can be used to reliably model path loss. SET2DIL data was collected for each test PCB. The foregoing test efforts were accomplished by utilizing seven different laminate systems to build the test PCBs. In order to eliminate any process-related issues, these test boards were built using the same artwork and the same fabricator at the same time. AUTHORS BIOGRAPHIES LEE RITCHEY Lee Ritchey is considered to be one of the industry s premier authorities on high-speed PCB and system design. He is the founder and president of Speeding Edge, an engineering consulting and training company. He conducts on-site private training courses for high technology companies and also teaches courses through Speeding Edge and its partner companies in public venues as well as at industry trade shows and technical conferences. In addition, he provides consulting services to top manufacturers of many different types of technology products including Internet, server, video display and camera tracking/scanning products. Prior to founding Speeding Edge, Ritchey held a number of hardware engineering management positions including Program Manager for 3Com Corporation in Santa Clara and Engineering Manager for Maxtor. Previously, he was co-founder and vice president of engineering and marketing for Shared Resources, a design services company specializing in the design of high-end supercomputer, workstation and imaging products. Earlier in his career, he designed RF and microwave components for the Apollo space program and other space platforms. Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior. In 2004, Ritchey contributed a column, PCB Perspectives which appeared on a monthly basis in the industry-renowned trade publication, EE Times. JOHN ZASIO John Zasio, co-author of "Right the First Time, A Practical Handbook on High Speed PCB and System Design," is an industry-recognized expert in high-speed design and serves as a Technical Advisor to Speeding Edge. He has more than 40 years experience in electrical engineering and his expertise spans a broad range of PCB, ASIC, gate array, standard cell, high-speed circuit and power subsystem designs. In addition to serving as a technical advisor to Speeding Edge he provides consulting services to a variety of technology firms in Silicon Valley. Previously, he served as a Technology Consultant on a number of high speed design projects and was responsible for IC design and packaging, PCB design rules, high-speed circuit design, EMI, power subsystems and testing for a variety of clients including AMP, Alpine Microsystems, Caspian and Intuitive Surgical. His earlier positions include serving as Chief Technologist for Hal Computer Systems; Executive VP of R&D for Aida Corporation; VP of Technology Development for STC Computer Research; VP of Engineering for Microtechnology Corporation; Manager of Electrical Engineering for Amdahl Corp.; Manager of Electrical Engineering for Mascor Corp. and Manager of Circuit Development for IBM Corporation. Zasio holds a B.S.E.E. from the University of Cincinnati and pursued graduate studies at Syracuse University. He holds 33 patents in the areas of high-speed circuit design, IC design, software design, verification tools, scan-based DesignCon 2013 High Speed Effects Page 2

3 test methodology, electron beam pattern generation, semiconductor test equipment and hardware simulation accelerators. RICH PANGIER Rich Pangier is the Director of OEM Marketing for Isola. Rich has been with Isola for 24 years starting with Norplex Oak in 1988 in La Crosse WI. Rich has held numerous positions within Isola including Field Applications Engineer, Sr. Account Manager and for the past 14 years Director of OEM Marketing. Rich is also the Product Manager for Isola s new very low loss product, I-Tera. Rich co-authored the paper Making Sense of Laminate Dielectric Properties which discusses the different Dk Df test methods, the effects of different material types and the data necessary in selecting materials for High Speed Digital Designs. Rich can be reached at Rich.Pangier@isolagroup.com GERRY PARTIDA Gerry Partida is the Director of Engineering for Marcel Electronics International in Orange California and has been with MEI since He began his career in the Printed Board industry in 1984 at Everett Charles Test Equipment, and joined Optrotech/Orbotech in He has been part of the team that introduced CAM automation, net list compare, and AOI Cad Reference. In his current position he focuses on cutting-edge high density interconnect, high speed digital and microwave printed boards for the military and commercial industries. He is a certified IPC trainer, and a member of the IPC-6012 and IPC-6018 review committees. He can be reached at Marcel Electronics International at gpartida@mei4pcbs.com DesignCon 2013 High Speed Effects Page 3

4 OVERVIEW As the speed of differential pairs has increased in recent years several phenomena have begun to degrade signal quality. Among these are glass weave-induced skew, losses from the dielectric and copper losses associated with trace surface area and roughness. There has been a great deal of work done to try to accurately model these effects. The results of these efforts have been mixed. In order to insure design goals are being met, engineers have been forced to build test PCBs to validate assumptions. Even with these methodologies, lot-to-lot consistency has been difficult to predict, primarily due to variations in PCB fabrication methods. This paper examines the effects of glass weave style on differential pair skew with a goal of arriving at the lowest cost method for controlling this phenomenon. It also examines the affect on dielectric loss of seven different laminate systems as well as how copper roughness affects loss. INTRODUCTION Test PCBs were built from seven different laminate systems using the same artwork and the same fabricator. All inner layers were etched at the same time on the same etching line to insure uniformity of process and all PCBs were laminated at the same time. The goal was to eliminate variables associated with constructing test PCBs at different facilities at different times. Each test PCB consisted of 16 total layers six of which were stripline layers, eight were plane layers tied together and two were outer layers. The stackup was symmetrical around the center. The upper three stripline layers were built with VLP (Very Low Profile) copper and the lower three stripline layers were built using standard reverse treat copper. Identical test traces were routed in each type of copper to allow quantifying the effect of copper roughness on overall loss. Figure 1 is a typical PCB stackup drawing for one of the test PCBs. Each test PCB was designed with both a daughter card connector and a backplane connector as shown in Figure 2. This was done to allow two PCBs to be connected together to form the typical daughter card-backplanedaughter card configuration found in large systems. Figure 3 shows two test PCBs plugged together. This allowed testing full differential paths with lengths ranging from 16 to 60 (41 cm to 152 cm) in any combination of the seven laminates used in this set of tests. This allowed actual testing of a wide variety of laminates to determine which combination satisfied a particular design challenge. The connectors used in this test are from the Amphenol EXCEED series. In addition, the SET2DIL test structures were included in each test PCB, one in the smooth copper and one in the rough copper so that loss values could be obtained using this test methodology. ISOLA I-TERA TEST PCB, 16 LAYERS, 9/10/12 Rev 5.0 Layer # Material Name Material Type Material Construction Copper Material Material Type S = Pressed Er Unpressed RTF, X = (at ~2 Thickness HVLP GHz) (mils) Material Pressed Thickness (mils) Picture Copper Copper Thickness Thickness (mils) (oz) Single Ended Trace Width (mils) Single Ended Imped. (ohms) Diff Pair Diff Pair Trace Spacing Diff Pair Width Gap Imped. (mils) (mils) (ohms) Trace Spacing Clearance Propagation (Non-Diff) Speed Loss Factor (mils) (ps/inch) (db/inch) Comments 0.7 Solder Mask 1 Top Surface Traces & Pads I-TERA Prepreg 2 x 3313 RC = 60% Prepreg 2 Ground X Plane I-TERA Core 1 x 3313 RC = 60% core Core 3 Sig 1 X Stripline I-TERA Prepreg 1 x 3313 RC = 60% Prepreg 4 GND X Plane I-TERA Core 1 x 3313 RC = 60% core Core 5 Sig 2 X Stripline I-TERA Prepreg 1 x 3313 RC = 60% Prepreg Core 6 GND X Plane I-TERA Core 1 x 3313 RC = 60% core Prepreg Core 7 Sig 3 X Stripline I-TERA Prepreg 1 x 3313 RC = 60% Prepreg 8 GND S Plane I-TERA Core 2 x 2116/2 x 1080 RC = 62% core Prepreg Core 9 GND S Plane I-TERA Prepreg 1 x 3313 RC = 60% Prepreg Core 10 Sig 4 S Stripline I-TERA Core 1 x 3313 RC = 60% core Prepreg Core 11 GND S Plane I-TERA Prepreg 1 x 3313 RC = 60% Prepreg Core 12 Sig 5 S Stripline I-TERA Core 1 x 3313 RC = 60% core Core 13 GND S Plane I-TERA Prepreg 1 x 3313 RC = 60% Prepreg 14 Sig 6 S Stripline I-TERA Core 1 x 3313 RC = 60% core Core 15 Ground S Plane I-TERA Prepreg 2 x 3313 RC = 60% Prepreg 16 BOTTOM c` Surface Traces & Pads 0.7 Solder Mask Material Copper Thickness Total Thickness Thickness FIGURE 1. TYPICAL PCB STACKUP DesignCon 2013 High Speed Effects Page 4

5 For those not familiar with the SET2DIL test method, it is a method for determining the overall loss of a particular PCB in a production environment. It is being standardized by the IPC. The seven laminate types used to construct the test PCBs included: Isola IS415 with 3313 weave e glass cloth Isola FR408HR with 3313 weave e glass cloth Isola FR408HRIS with 8313 low DK glass cloth Isola I-SPEED with 3313 weave e glass cloth Isola I-SPEED with 8313 low DK glass cloth Isola I-TERA with 3313 weave e glass cloth Isola I-TERA with 8313 weave low DK cloth (DK is often used instead of e r ) E glass cloth is cloth woven from a glass formulated to optimize manufacturability. It is the most common glass used for woven cloth used to manufacture PCB laminate. Low DK glass is a glass formulated to produce a cloth whose relative dielectric constant (DK) is lower than that of e glass. FIGURE 2. A TYPICAL TEST PCB BACKGROUND: WEAVE INDUCED SKEW IN DIFFERENTIAL PAIRS The problem of skew between the two sides of a differential pair caused by the irregular distribution of glass in the cloth weaves used in most common laminates has been described in several papers presented at previous DesignCon conferences. Reference 2 of this paper describes the problem along with some possible solutions. Figure 4 shows two of the glass styles used to create PCB laminates 1080 and The 1080 glass weave has been the most commonly used weave in the popular low loss laminates utilized in very high speed applications. Differential skews as large as 130 psec have been reported using this glass weave. In this figure, a 3.5 mil (89 micron) wire has been superimposed on the two laminates to lend scale to the traces commonly routed on inner signal layers. DesignCon 2013 High Speed Effects Page 5

6 As can be seen, the 3.5 mil wire or trace often travels at an angle across the weave. In the case of the 1080 weave, it can be seen that the trace passes over a bundle of glass with an e r of around six and between the two bundles, where it is surrounded by mostly resin, with an e r of less than 3. When this happens two effects are observed. First, the impedance will vary locally, higher in the regions of low e r and lower in regions of high e r. Second, the velocity will increase where the e r is low and decrease where the e r is high. Figure 5 shows the impedance variations along the length of a trace of uniform trace width travelling over the two types of glass weave shown in Figure 4. FIGURE 3. A TYPICAL TWO BOARD TEST PCB CONFIGURATION 1080 GLASS WEAVE 3313 GLASS WEAVE FIGURE 4. TWO GLASS WEAVE STYLES USED TO CREATE LAMINATE WITH A 3.5 MIL WIRE DesignCon 2013 High Speed Effects Page 6

7 1080 GLASS WEAVE 3313 GLASS WEAVE FIGURE 5. IMPEDANCE vs. FREQUENCY FOR A TRACE ON TOP OF GLASS WEAVES IN FIGURE 4 SOME GLASS WEAVE STYLES AND THEIR PROPERTIES There is a wide range of glass weave styles available with which to create the laminate along with the prepreg used to fabricate PCBs. Figure 6 depicts several other glass weave styles with 3.5 mil wires to give perspective. It can be noted that the fibers on the bundles of glass in the 106 and 1080 glass weaves are tightly spun leaving large voids between them filled with resin. The glass bundles in the 1067 and 1086 glass weaves (shown in Figure 6 replacements for 106 and 1080, respectively) are spread out, which resulted in a uniform distribution of glass across the entire surface. This spreading was done to facilitate the drilling of blind vias with lasers to improve via reliability. A side benefit is that it substantially reduced skew in differential pairs. (1078 is an alternate spread weave and 8313 is a low DK weave used in these test PCBs.) The 2116 weave appears to have evenly spread the glass across the surface. Unfortunately, the size of the glass bundles is such that irregular distribution of glass results has been found to produce skew problems. 106 WEAVE 1067 WEAVE DesignCon 2013 High Speed Effects Page 7

8 1086 WEAVE 2116 WEAVE 1078 GLASS WEAVE 8313 GLASS WEAVE FIGURE 6. SEVERAL GLASS WEAVE STYLES USED IN LAMINATES Table 1 shows a variety of glass weaves and the degree to which they are spread as well as whether the spreading has been done in both the X and Y axes (MS Spreading-mechanical spreading) and 1086 exhibit the most uniform spreading and result in lowest skew. Some weavers of 3313 mechanically spread the glass in both the X and Y axes. In the skew tests listed below in Table 1, the 3313 and 8313 glasses were mechanically spread in only the Y direction. In the tests results shown in Figures 5 for 3313, the glass was mechanically spread in both the X and Y directions. Glass Styles Square? Expanded? Spread? MS Spread? 106 Yes No No No 1067 Yes Yes Yes Yes 1080 No No No No 1086 Yes Yes Yes Yes 2113 No Yes Yes No 2313 No Yes Yes No 3313 Yes Yes Yes No 2116 Yes No No No 1652 Yes No No No 7628 No No No No Courtesy of Isola Corporation TABLE 1. SPEADING CHARACTERISTICS OF VARIOUS GLASS WEAVES DesignCon 2013 High Speed Effects Page 8

9 POTENTIAL SOLUTIONS TO WEAVE INDUCED SKEW PROBLEM Several solutions to the irregular weave problem have been proposed. Among these are: Route signals at an angle to the glass weave as proposed in reference 2. Build each PCB on the fabrication panel at an angle to the glass weave in the laminate. Route each member of a differential pair on the same pitch as the glass fibers so they experience the same irregularities. Use a glass that has a lower dielectric constant to reduce the difference between the resin and the glass. Use a glass weave style that has the glass spread out in a uniform manner as with 1067, 1086 and some versions of Each of the solutions listed above has merits and deficiencies. For cost reasons, it would be desirable to determine which of them adds the least cost to a PCB. MERITS OF THE ABOVE SOLUTIONS TO THE SKEW PROBLEM As with most things in life, very few things are free. This is true for all five of the solutions noted above. Each has advantages and each has disadvantages. Listed below are the known advantages and disadvantages of each solution. ROUTINGA SIGNAL AT AN ANGLE TO THE GLASS WEAVE During fabrication, PCBs are oriented on rectangular panels in such a way that the material is most efficiently used. This normally results in the traces on the PCB, which are usually routed in X and Y directions, being aligned with the glass fibers in the cloth used to create laminate which are also oriented in the X and Y directions. Because of micro distortion of the cloth, the condition shown in Figure 5 can result. Studies reported in Reference 2 revealed that if the traces are purposely routed at an angle to the glass weave, skew is minimized and this is true. Routing traces at an angle to the X and Y axes of the PCB is often difficult and sometimes impossible due to various constraints, such as high pin count BGAs. When it is possible, this routing method takes up more board space which results in larger PCBs. Therefore, this method has the potential of increasing PCB cost as well as adding to the time required to design the PCB. POSITIONING THE PCB ON THE FABRICATION PANEL AT AN ANGLE The second method proposed to avoid weave-related skew is to have the fabricator build each PCB at an angle to the weave in the glass. This involves rotating the artwork on the panel as shown in Figure 7. This method has been required by some OEMs and is patented by one of them. This method solves the skew problem. However, it is not without cost, noted by the red shaded material that is lost during fabrication resulting in a higher cost PCB. PCB ROTATED IN PRODUCTION PANEL RED IS WASTED MATERIAL FIGURE 7. PCB ARTWORK ROTATED AT AN ANGLE TO THE FABRICATION PANEL DesignCon 2013 High Speed Effects Page 9

10 ROUTE EACH MEMBER OF THE DIFFERENTIAL PAIR ON THE SAME PITCH AS THE GLASS WEAVE Routing each member of the differential pair on the same pitch as the glass fibers in the weave has been proposed as a way to cause each member to experience the same irregularities hopi hoping ng that the skew will be minimized. Figure 8 illustrates the dimensions in a glass weave as well as the pitch of the threads in each direction di for several commonly used glass cloths. X3 and d Y3 are the pitch of the individual bundles of fibers. Notice that the pitch is quite large compared to the dimensions of a trace and is not always the same in the X and Y directions. If the routing of the differential pairs is forced to the pitch of the bundles of fibers it may be difficult, if not impossible, impossible to route pairs through connector and BGA pin fields. The differential pairs in these test PCBs were routed at approximately the pitch of the glass fibers in the 3313 glass fabric. As can be seen in Table 2, the horizontal pairs have far greater skew than the vertical pairs. This suggests that such a routing strategy does not work when the glass weave has not been mechanically spread. Glass Fabric / X1 Measurement Results (mils) X2 X3 Y1 Y Y3 Data courtesy of Isola Corporation FIGURE 8 8.WOVEN GLASS FIBER DIMENSIONS USE A GLASS WEAVE WITH A DIELECTRIC CONSTANT SIMILAR TO THAT OF THE RESIN SYSTEM The glass usually used to weave glass cloth for PCB laminates and prepregs has a relative dielectric constant of about 6 and is referred to as e glass.. The relative dielectric constant of the most common resin systems is 3 or less. This wide difference accounts for the variations of impedance and velocity illustrated in Figure 5. Some of the test PCBs were constructed with low DK glass. These are FR408HRIS, II-SPEED SPEED with 8313 glass and I-TERA with 8313 glass. Table 2 shows skew measurements for all seven test PCBs. As can be seen in the vertical skew section, there is a minor reduction in average skew as a result of lowering the dielectric constant of the glass. However, the change does not seem large enough to warrant using such a specialty glass. The difference between etween vertical and horizontal skew is far larger and is caused by the manner in which the glass fibers are spread out. TEST PCB SKEW DATA, psec 6 SAMPLES MATERIAL WEAVE IS FR408HR 3313 FR408HRIS 8313 I-SPEED 3313 I-SPEED LOW DK 8313 I-TERA 3313 I-TERA LOW DK 8313 VERTICAL 9" MINIMUM MAXIMUM AVERAGE MINIMUM HORIZONTAL 14" MAXIMUM AVERAGE TABLE 2. SKEW MEASUREMENTS FOR SEVEN TEST PCBs DesignCon 2013 High Speed Effects Page 10

11 USING A GLASS WEAVE MECHANICALLY SPREAD IN BOTH X AND Y DIRECTIONS (WARP AND WOOF) In Table 2, the Horizontal skew is far larger than the Vertical skew, even with the laminate made from low DK glass. The reason for this is the fact that the glass is not mechanically spread in the horizontal or warp direction and it is in the vertical or woof direction. This can be seen in Figure 4. The test results from Figure 4, as shown in Figure 5, seem to indicate that the glass is uniformly spread in both the X and Y directions. As it happens, the laminate used in Figure 5 happened to be uniformly spread in both directions. This is not necessarily going to happen in all samples of 3313 or 8313 glass cloth. Mechanically spreading the glass fibers in both the X and Y directions results in very low skew without the need to do any special routing of the members of a differential pair such as routing on an angle, fabricating the board at an angle on the panel or using special glass types. Clearly, this should be the least expensive way to solve the differential skew problem. As it turns out, there are several glass weave styles that are spread in both the X and Y directions. Among these are 1067 and 1086, which are perfect candidates for replacing the 106 and 1080 glass styles. EFFECT OF SURFACE ROUGHNESS ON LOSS Several papers have been presented that make the case that the roughness of the copper on a trace and its adjacent plane can have a direct effect on overall path loss at high frequencies. Figure 9 shows the loss versus frequency curves for two PCBs made from the same material and the same artwork at two different fabricators. At 8 GHz the loss for the board on the left is 35 db and the loss for the board on the right is 40 db. They are substantially different, even though both boards were made using the same laminate and the same artwork. How could they be so different? FIGURE 9. LOSS vs. FREQUENCY FOR TWO PCBS DesignCon 2013 High Speed Effects Page 11

12 FIGURE 10.CROSS SECTION OF THE TWO PCBs IN FIGURE 9 Figure 10 shows the difference in copper surface roughness of the two PCBs in Figure 9. Notice that the copper roughness of the customer oxide is much greater on the left side of Figure 10 than the right side. This difference in surface roughness is due to the different ways that the two fabricators treated the surface of the traces and planes prior to lamination. Until recently, the primary driving force for copper roughness at a fabricator was the need to ensure delamination did not occur during assembly. To prevent delamination, the copper surface was made rough enough to insure good adhesion between the resin in the prepreg and the copper of the planes and traces. The fabricator on the right in Figure 10 must have had a history of delamination and created a far rougher surface than the fabricator on the left side. A second copper roughness variable is the finish on the surface as provided by the foil manufacturer. Table 3 shows the difference in loss as measured by the SET2DIL method for the smooth and rough traces designed into the test PCBs used for this report. The smooth copper is called HVLP by the foil supplier and the rough copper is called reverse treat. (By processing all of the inner layers of all the test PCBs on the same inner layer processing line at the same time, the customer oxide side was the same for all test vehicles and the differences are due to the foil roughness as supplied.) Figure 11 has cross sections of the foils as built into each test PCB. The left side is HVLP copper foil and the right side is reverse treat copper foil. Material Type Test Point Loss (db/inch) - 4GHz Loss (db/inch) - 8GHz Impedance IS Smooth Rough ITERA 8313 Smooth Rough HR 3313 Smooth Rough ISPEED 3313 Smooth Rough ITERA 3313 Smooth Rough TABLE 3. LOSS PER INCH FOR SMOOTH vs. ROUGH COPPER FOILS USING SET2DIL TEST DesignCon 2013 High Speed Effects Page 12

13 HVLP FOIL REVERSE TREAT FOIL FIGURE 11.FOIL ROUGHNESS OF TEST VEHICLES The surface treatment done by the fabricator is the same for both foil types. As can be seen in Table 3, there is a significant variation in loss due only to the surface roughness of the copper on the trace and plane layers. This is attributable to the finish on the copper foil as supplied by the foil manufacturer. ACCURACY OF LISTED DIELECTRIC CONSTANT VALUES Table 4 is a list of the relative dielectric constants of the seven laminate types used in these tests with the DK or er shown as published by the supplier and as measured using the test PCBs. Also included is the predicted impedance using these values along with the measured impedance on the test PCBs. There is very good agreement of DK in all boards other than those built using standard I-TERA. Checking revealed a typographical error with this material. The actual value from the supplier is 3.54 for this material. The impedance variations are the result of artwork discrepancies. DIELECTRIC CONSTANT AND IMPEDANCE TEST DATA DIELECTRIC CONSTANT IMPEDANCE, OHMS PUBLISHED MEASURED MATERIAL VALUE VALUE PREDICTED MEASURED IS FR408HR FR408HRIS I-SPEED I-SPEED LOW DK I-TERA I-TERA LOW DK TABLE 4. DIELECTRIC CONSTANT AND IMPEDANCE MEAURED VALUE AGAINST PUBLISHED VALUES VARIATION IN DIELECTRIC CONSTANT AS A FUNCTION OF COPPER SURFACE ROUGHNESS At a previous DesignCon conference, a paper was presented that indicated the roughness of the copper had an effect on the dielectric constant of a laminate. Table 5 is a measure of the DK of the seven materials used in these experiments showing the measured DK for both the smooth and rough copper. These test results are consistent with the previous study. However, the variation is quiete small and is within the variation found in these materials as produced from lot to lot. DesignCon 2013 High Speed Effects Page 13

14 Smooth Rough Laminate Glass Weave Er Er IS415 Std E FR408HR Std E FR408HRIS Low DK I-SPEED Std E I-SPEED Low DK I-TERA Std E I-TERA Low DK TABLE 5.DIELECTRIC CONSTANT vs. SURFACE ROUGHNESS SUMMARY Skew in differential pairs is, indeed, a potential source of signal degradation in very fast signal paths. Of all the proposed methods for minimizing this problem, controlling the glass weave used to manufacture the laminate is the lowest cost solution. In fact, these glass weaves are commonly available from most sources at no cost premium over the weaves they replace. Copper roughness has also been shown to have a significant effect on the overall loss of a high speed signal path. There are two places where copper roughness can affect this loss. The first is in the manufacture of the foils used to create the laminate. The second is during the fabrication process as the inner layers are prepared for lamination. The current method for documenting a PCB for the fabricator provides no means for controlling either glass weave style or surface roughness. It is necessary to provide a stackup drawing similar to that shown in Figure 1 as well as fabrication notes that specify the manner in which a fabricator prepares inner layers to be assured of consistency from lot to lot and fabricator to fabricator. Fabricators accustomed to manufacturing PCBs for the high performance market are accustomed to this type of requirement. The good news is there are well understood methods for controlling both skew and loss. However, it is important that this information be properly communicated to the PCB fabricator to insure these methods are incorporated into the final PCB product. Further, it is important to put in place appropriate checks at receiving inspection to insure the PCBs are correctly fabricated. DesignCon 2013 High Speed Effects Page 14

15 ACKNOWLEDGEMENTS Special thanks to the following: Kella Knack for her editorial skills in making this paper readable. Isola Corporation for supplying all of the laminate materials to construct these test PCBs Isola Analytical Services Laboratory MEI for fabricating the test PCBs. Amphenol for supplying the backplane and daughter card connectors. Paul Hathaway, Amphenol Corporation DesignCon 2013 High Speed Effects Page 15

16 REFERENCES 1. Zasio, John, Rogers Test Board TDR Analysis, December 11, McMorrow, Scott etal, Impact of PCB Laminate Weave on Electrical Performance, DesignCon, Fall Ritchey, Lee W. A Way to Address the Problem of Jitter and Skew in Gigabit and Faster Signals Caused by Laminate Weaves, Current Source, June Bogatin, Eric, Skewering Skew, Laminate Weave Induces Skew, Printed Circuit Design, April Horn, Allan, etal, Effect of Conductor Profile on Insertion Loss, DesignCon January DesignCon 2013 High Speed Effects Page 16