1.0μm 40V HV 1.0 Micron 40V High Voltage CMOS Technology for high voltage Product Applications

Transcription

1 1.0μm 40V HV 1.0 Micron 40V High Voltage CMOS Technology for high voltage Product Applications Overview 10HV is one of CSMC s high voltage process platforms. It is a simple high voltage process with a few masking layers. In addition to dual gate oxide, double metal and 1.0 micron drawn gate length process for digital applications, process modules are available for 5 volt drain-source, isolated transistors and high resistance poly resistors and zener diode. For getting a small digital circuit size, CSMC can provide 0.5um backend design rule for 1.0um 40V HV CMOS process. All main modules are comparable in Design Rules. Comprehensive design rules, accurate SPICE models, DRC and LVS common file support the process on platforms supplied by the major EDA tool vendors Key Features - 5V logic layout & performance compatible with the industry standard micron single metal front-end, 1.0um or 0.5um back-end - Epi process for isolated devices - Modular concept (HR/ Zener / BJT / Special require) - 5V/40V HVCMOS and 40V/40V HVCMOS - High value poly resistor - I/O cell library with 2KV HBM ESD protection levels - Typical and worst-case models: BSIM3v MOS; sub-circuit model----res&cap Applications - LCD driver - LED driver - Power management product - Battery protection IC - CCFL inverter Quality Assurance CSMC continue to improve the process quality and reliability and to provide competent support to the customers. CSMC follow APQP procedures developed process technology. This comprehensive, proprietary quality improvement system has been certified to fulfill the requirements of the ISO 9001, QS 9000, ISO TS and other standards. Deliverables PCM tested wafers Optional production services: wafer probe sort Optional production services(turn key): packages and final sort Optional Engineering services: Multi Project Wafer (MPW) and Multi Layer Service (MLM)

2 Briefly Process Flow MOS Module N bury layer N-well Active area NF photo implant HV thick gate oxide Poly1 N+ Implant P+ Implant Contact Metal 1 Via 1 Metal 2 PAD Additional Module Poly high resistor Zener photo and implant Schematic Cross Sections N-channel LV MOS P-channel LV MOS P+ N+ N+ N+ P+ P+ P-substrate HV Symmetric NMOS HV Asymmetric PMOS P+ N+ N+ P+ N+ P+ P+ N+ BN

3 HV Symmetric PMOS HV Asymmetric NMOS N+ P+ P+ N+ P+ N+ N+ P+ BN P-substrate Zenner diode HV Isolated NMOS N+ P N+ P+ N+ Zenner P+ N+ N+ P+ BN+ BN+ Document list Mask Tooling Information Electrical Design Rule PCM Specification SPICE model DRC LVS common file Basic Design Rules Basic design rules Parameter Width(µm) Space(µm) Pitch(µm) N bury layer N well Active Poly gate Basic design rules of 1.0um back-end process Parameter Width(µm) Space(µm) Pitch(µm) N P Contact M Via Top Metal (Thin) Basic design rules of 0.5um back-end process Parameter Width(µm) Space(µm) Pitch(µm) N P Contact M Via Top Metal (Thin / Thick) 0.7 / / / 2.4

4 Key Device Parameters MOS Transistor Device Device name VT (V) Ids (ua/um) Bvd/sgt (V) Ioff (pa/um) Max. Vds Max.Vgs normal NMOS NMOS >9 < normal PMOS PMOS <-9 < Thick GOX HV Asy NMOS HV Asymmetric NMOS >46 < Thick GOX HV Sy NMOS HV Symmetric NMOS >46 < Thick GOX HV ISO NMOS HV Isolated NMOS >32 < Thick GOX HV Asy PMOS HV Asymmetric PMOS <-46 < Thick GOX HV Sy PMOS HV Symmetric PMOS <-46 < thin GOX HV Asy NMOS HV Asymmetric NMOS >46 < thin GOX HV Sy NMOS HV Symmetric NMOS >46 < thin GOX HV ISO NMOS HV Isolated NMOS >40 < thin GOX HV Asy PMOS HV Asymmetric PMOS <-46 < thin GOX HV Sy PMOS HV Symmetric PMOS <-46 < BJT Transistor Device Device name Hfe BVceo (V) BVcbo (V) BVebo (V) Parastic VNPN npn 220 >9 >25 >10 Parastic VPNP pnp 57 <-9 <-22 <-14 Resistor and conductors Device Device name Rs(ohm/sq) Thickness(um)/junction depth(um) N well 100/10 Res N well P well 100/10 Res P well N+ 100/10 Res N+ Res P+ 100/10 Res P+ Res P+ imp Poly 100/10 Res Poly Res N+ imp Poly 100/10 Res Poly Res none imp Poly 100/10 Res Poly Res Poly1 80/10 high Res Poly Res Capacitors Device Device name Area Cap.(fF/um2) BV (V) Thin GOX/NW CAP MOS CAP 1.52 >15 Thin GOX/PW CAP MOS CAP 1.57 >15 Thick GOX/NW CAP MOS CAP 0.36 >70 Thick GOX/PW CAP MOS CAP 0.37 >70 Examples for measured and modeled parameter characteristics Figure1. NMOS W/L=20/1.0 Figure2. PMOS W/L=20/1.0

5 Figure3. HV Thick GOX Asy NMOS Figure4. HV Thick GOX Asy PMOS Figure5. HV Thick GOX Sy NMOS Figure6. HV Thick GOX Sy PMOS Figure7. HV Thick GOX ISO NMOS Figure8. HV Thin GOX ISO NMOS

6 Figure9. HV Thin GOX Asy NMOS Figure10. HV Thin GOX Asy PMOS Figure11. HV Thin GOX Sy NMOS Figure12. HV Thin GOX Sy PMOS