Enabling Requirements Engineering for Real-Time Critical Systems with Rational DOORS and INCHRON Tool-Suite. Uwe Brodtmann, CEO INCHRON

Transcription

1 Enabling Requirements Engineering for Real-Time Critical Systems with Rational DOORS and INCHRON Tool-Suite Uwe Brodtmann, CEO INCHRON June 6, 2013

2 INCHRON GmbH Company History 1996: Start of fundamental research 2003: INCHRON founded 2006: Investment from Hasso Plattner Ventures 2009: Premium Member AUTOSAR 2011: Global Reseller Agreement IBM Rational Partners Customers Memberships 2

3 Timing Requirements from Different Views Trigger System reaction Real-Time Requirement of vehicle function t?? Read control value Real-Time Requirement of control algorithm Control value output t Sensor/Actuator Bus Messages Performing SW-components Detailed definition of timing requirements consideration of all involved components t COM-Layer Signal Process. Controller 3

4 FPGA I/O INCHRON GmbH 2013 A V-model perspective on timing Signal detection Object Verification Decision Specification Braking Detection of timing errors Preprocessing Tracking Timing Requirement: t 300 ms Signal detection Preprocessing Design Object Verification Tracking Decision Integration & Test Braking Timing Requirement: t 300 ms Implementation 4

5 FPGA I/O INCHRON GmbH 2013 Levels in E/E-Systems Vehicle Domain ECU Software 5

6 FPGA I/O FPGA I/O INCHRON GmbH 2013 E/E-System for a Driver Assistence System Vehicle Domain ECU Software 6

7 FPGA I/O INCHRON GmbH 2013 E/E-System Multiple Suppliers OEM Tier1 Tier1 7

8 Function Network Vehicle Movement Signal detection Object Verification Decision Braking Preprocessing Tracking Timing Requirement: t 300 ms 8

9 FPGA I/O INCHRON GmbH 2013 Event Chain in E/E-System Vehicle Movement Signal detection Preprocessing Object Verification Tracking Decision Braking Timing Requirement: t 300 ms 9

10 Limited System View of OEM OEM 10

11 FPGA I/O INCHRON GmbH 2013 Limited System View of Tier 1 Tier1 t 250 ms t 50 ms 11

12 FPGA I/O, Bus FPGA I/O, Bus INCHRON GmbH 2013 Multiple Suppliers of SW Components OEM Tier1 Tier1 Tier2 12

13 Event Chain on Time Axis Tier1 time 13

14 Tier 1: Event Chain Evaluation Tier1 time 14

15 Tier 1: Event Chain Evaluation Tier1 time 15

16 Tier 1: Event Chain Evaluation Tier1 Event chain broken Data lost Timing Requirement: t 250 ms Failed! time 16

17 Tier 1: Event Chain Evaluation Tier1 Preemption by other task Clock drift and delayed by other task time 17

18 Event Chain Evaluation End-to-End Tier1 OEM Tier1 time 18

19 INCHRON GmbH 2013 Timing Model of Dynamic System Behavior FPGA I/O, Bus T n T m T o T p Timing-Model 19

20 System Architecture and Requirements Real-Time Data Sheet and Bus Load Event Chain Latencies Event Chain Synchronization Signal Rate, Loss or Age Runnable s Response Time Runnable s Execution Rate and Order Runnable s Activation Condition IRQ s Loss or Blocking T n T m T o T p Timing-Model Real-Time Data Sheet and Bus Load Event Chain Latencies Event Chain Synchronisation Signal Rate, Loss or Age Runnable s Response Time Runnable s Execution Rate and Order Runnable s Activation Condition IRQ s Loss or Blocking 20

21 Real-Time Data Sheet in Early Design Phase Real-Time Data Sheet Tier1 OEM and Bus Load Event Chain Latencies Event Chain Synchronisation Signal Synchronisation Rate, Loss or Age Runnable s Signal Rate, Response Loss or Age Time Runnable s Execution Response Rate Time and Runnable s Order Execution Rate Runnable s and Order Activation Condition Runnable s Activation IRQ s Condition Loss or Blocking IRQ s Loss or Blocking T n T m T o T p Timing-Model Tier1 Tier2 Tier2 Tier2 21

22 FPGA I/O INCHRON GmbH 2013 Continuous Integration and Test Tier1 Real- Time Data Sheet Timing- Model Timing- Model Real- Time OEM Data Sheet Tier1 Tier2 Tier2 Tier2 Real- Time Data Sheet Real- Real- Time Time Time Data Data Data Sheet Timing- Model Timing- Timing- Timing- Model Model Model 22

23 FPGA I/O INCHRON GmbH 2013 Continuous Integration and Test Tier1 Tier1 Tier2 Tier2 Tier2 Real- Time Data Sheet Real- Time Data Sheet Timing- Model Timing- Model Timing- Timing- Timing- Model Model Model Real-Time Data Sheet and Bus Load Event Chain Latencies Event Chain Synchronization Signal Rate, Loss T or Age n T m Runnable s Response Time Runnable s Execution Rate and Order Runnable s Activation Condition IRQ s Loss or TBlocking o T p Timing-Model Timing- Model Real- Real- Time Time Time Data Data Data Sheet Real- Time OEM Data Sheet 23

24 FPGA I/O INCHRON GmbH 2013 A V-model perspective on timing Signal detection Object Verification Decision Specification Braking Detection of timing errors Preprocessing Tracking Timing Requirement: t 300 ms Model-based analysis and simulation Signal detection Preprocessing Design Object Verification Tracking Decision Integration & Test Braking Timing Requirement: t 300 ms Implementation 24

25 Integration: Rhapsody chronsim DOORS System in UML UML-Profile DOORS Data + SW/HW- Architecture + Execution Times + Stimulation Timing Model T n T m Requirement Status Roundtrip to DOORS DOORS Req. T o Dynamic T p Behavior 25

26 Integration: Rhapsody chronsim DOORS System in UML Modeling functional and dynamic behavior in Rhapsody UML-Profile One model no consistency problems Timing and performance analysis of dynamic architecture Sensitivity analysis on dynamic behavior + SW/HW- Architecture + Execution Times + Stimulation Timing Model T n T m What-if analysis for design alternatives Impact analysis for change requests Managing functional and timing requirements in DOORS Improve product quality Evaluate requirements model based DOORS Req. T o Dynamic T p Behavior 26

27 Modeling External Stimulation Flexible Stimulation Patterns for Tasks and ISRs 27

28 Modeling Tasks and ISRs Scheduling Parameters Definition of Tasks and ISRs 28

29 Modeling Functions and Net Exec. Times Task Net Execution Times Function Net Execution Times Function Execution Order and Condition 29

30 Allocation of Tasks and IRQs to Resources HW Resources Tasks and ISRs Allocation 30

31 Simulation of Dynamic Behavior Process State Diagram Task Response Time Histogram Process Timing Box-Plot Load Diagram 31

32 Requirements Interchange via OSLC Read text based requirements from DOORS Add formal, technical requirements for timing and performance

33 Evaluate Requirements in Real-Time Simulation Requirement Histogram Bad and Good Cases 33

34 Requirements Interchange via OSLC Read text based requirements from DOORS Add formal, technical requirements for timing and performance Simulate, analyze and test Feed results back to DOORS

35 Real-Time Requirement Analysis Requirements analysis live and in html-report Html-Report Detailed summary of system timing Profile for each process, task, ISR Document with links and diagrams Statistics with histograms 35

36 Integration: Rhapsody chronsim DOORS System in UML No entry hurdles Import of OIL files, modeling in C First usable results produced after only two days Very short turnaround times UML-Profile Total time effort for this project approx. 2 weeks DOORS Data + SW/HW- Architecture + Execution Times + Stimulation DOORS Req. "The feasibility of such change requests can now be analyzed in 1/3 of the usual time. This saves time and money, allows fast feedback to the customer and gives more confidence in the modified system. Timing Model Requirement Status chronsim T n Tis m a valuable tool. Without, several problems fixed would still be present in our system today. It took us only 10 days of training and occasional consulting to Tget o Dynamic to Ta p very Behavior high level of expertise Support from INCHRON has always been excellent. The tool was worth the investment. We have found errors already in simulation, that we would have found 12 months later in testing. Undisclosed Tier 1 36

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39 Thank You! INCHRON August-Bebel-Str Potsdam Germany Tel Fax