Mobile Device Passive Integration from Wafer Process

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1 Mobile Device Passive Integration from Wafer Process Kai Liu, YongTaek Lee, HyunTai Kim, and MaPhooPwint Hlaing STATS ChipPAC, Inc West Greentree, Suite 117, Tempe, Arizona 85284, USA Tel: Abstract In this paper, we present some passive components made from silicon substrate technology (Integrated Passive Device process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process are characterized on ESR and ESL performance. Functional blocks (filters, baluns, diplexers, matching, etc) made from the IPD process, have shown good electrical performance with small form-factor features. The thin profiles from the IPDs make them very suitable to be used inside laminate and QFN packages. System-in-Packages or multiple-chip-modules using IPD approaches may have significant size reduction. The low profiles and the small form-factors of the IPDs result in less cross-talk between the IPDs and their nearby components (chips, SMDs, and routing traces, etc), and therefore it is easier to maintain signal integrity for packages. Key words: RF, integrated passive device, system-in-package, and small form-factor INTRODUCTION Small form-factors along with other features (light-weight, low-loss, etc.) are the key enablers for mobile devices. New generation of semiconductor technology (e.g., 25 nm node technology) has reduced the transistors sizes tremendously, which is fairly predicted by Moore s law. However, this scaling innovation has less impact on passive devices, which are consist of 6% to 7% of an electronic product (system or subsystem or SiP package). Traditional passive devices, some times called SMD components, are made of ceramic technology. These SMD parts have been widely used in many electronic products, such as computers, cameras, cellular phones, wireless communication devices, etc. In the foreseeing future, these components will be still dominant in electronic applications. LTCC parts are the major sources for RF or/and high power applications, because of their superior RF and thermal properties. Functional blocks, such as baluns, filters, diplexers, from LTCC technology, have better tolerance and usually also have smaller form-factors than using discrete SMD components. 878

2 Passive functions, such as inductance, resistance, capacitance, can be also realized and embedded in laminate substrates. The substrates are not only used as supporting materials and for routing purposes, but also they are having electrical functions through the embedded passive parts. Dramatic foot-print saving may be realized by embedded passive approaches, since there is no need to populate SMD components for passive functions on laminate surface or boards any more. Another passive device realization is from wafer processes. Similar to the BEOL processes used in the semiconductor industry, passive components can be made through thin-film processes. Highly repeatable RCL components with tight tolerance may be made in these processes using silicon, GaAs, glass, or other substrates [2-6] INDUCTOR AND CAPACITOR In the wafer process for passive devices, there are metal layers, M1,, and M3 covered by passivation layers (PI-1 and PI-2). Inductor coils are made in thick Cu layer (M3) through plating process. Capacitors are made between Al layers (M1 and ) using silicon nitride substrate. Resistors are made in TaSi layer with sheet resistance of 8. Ohm/square. To overcome metal loss for inductors, the thickness of inductors should be large enough. But it is not cost-effective to make very thick metal layer though the wafer plating process. In order to find an optimal metal thickness, given this technology (substrate and material set-up), a set of simulations for a 2.2 nh inductor were carried out and the data is plotted in Figure 2. From the figure, the inductor with 2. um thickness shows decent, but not enough Q. When the thickness reaches 8. um, the inductor Q peak starts to saturate. It concludes that inductor thickness of 8. um - 1. um should be the best approach for RF performance while considering waferprocess efficiency. Q factor Metal Thickness=2um, 4um, 6um, 8um Figure 2: IPD inductor (2.2 nh) Q-factors for different metal thickness. INDUCTOR M3 M3 M3 oxide CAPACITOR M1 silicon substrate nitride TaSi RESISTOR PI-2 PI-1 TaSi nitride Figure 1: Cross-section of integrated passive device. The IPDs can be made either in wirebonding configuration (device facing up) or in flip-chip configuration (device facing down). The same inductor layout for these two configurations will have slightly different response in terms of inductance and Q factor. In wire-bonding configuration, the inductor Q and inductance are mainly affected by the distance to GND, usually the thickness of the silicon substrate. In flipchip configuration however, they are mainly 879

3 impacted by the bump stand-off height (assuming the top metal layer in laminate substrate as ground plane). Inductance (H) 5E-9 4E-9 3E-9 2E-9 1E-9 Stand off=75um, 1um, 125um Q factor For some RF passive circuits, because they will be used together with active devices (RF power amplifier, transceiver, for example), DC power supplier lines could pass through these passive devices. Figure 4 shows a GSM balun with a power-line fed through the balun to the differential ports on the left. Figure 3: Inductance and Q-factor for a 2.2 nh inductor in flip-chip configuration. Figure 4: Decoupling capacitors used for RF integrated passive device (balun). The inductance and Q factor with different bump stand-off heights were simulated and depicted in Figure 3 for a 2.2 nh inductor. For bump stand-off from 75. um to 125. um, the Q changes from about 34. to 38.. For RF performance, this is not significant. But the inductance value is changed about.3 nh, which is about 13.6% of the target inductance (2.2 nh). For RF circuits, a 13.6% change of inductance value may cause significant performance degradation. Making bump stand-off higher for RF performance would require bigger bumps and therefore larger IPD size, which will in turn raise cost concerns. From our investigation as shown in Figure 3, as long as the bump stand-off is not less than 125. um, typical inductors performance is stable. The capacitance density from the wafer process is around a few hundreds pf/mm 2. This capacitance density is good enough for RF circuits where needed capacitance is not very large (usually in.5 pf to 1 pf range), but may not enough for regular decoupling purposes for power suppliers. Without proper decoupling, RF signal (in GHz band) could be coupled to the power supplier line, and then propagate and interfere with other function blocks in the same IPD. To minimize the interference, RF decoupling capacitors can be used. ESR (effective-series-resistance) and ESL (effective-series-inductance) are the figures of merit for decoupling capacitors. In Figure 5, three interconnection layouts for a capacitor are shown, to evaluate ESR and ESL performance. For each case, the interconnection length is the same, but the width is different. In case 3 ( CAP3 ), one electrode of the capacitor is connected by trace approaching from the wider side of the capacitor. The ESR and ESL data are summarized in Table 1. By different interconnection designs, the ERS can be reduced to 6%, and ESL can be reduced to 55%. 88

4 principle, will be reduced. An IPD design facing from the reduced inductor Q, may be optimized to achieve almost equally good performance as using LTCC approaches, given the facts of shorter interconnection, less parasitic, and easier optimization adoption associated with the IPD technology [1][3]. Figure 5: Three capacitor layouts with the same intrinsic capacitance (12pF). Table 1: RF decoupling capacitor Capacitor_1 Capacitor_2 Capacitor_3 ESR (m Ohm) ESL (nh) Freq (resonate freq, GHz) Capacitance (pf) PASSIVE FUNTIONAL BLOCKS Passive functional blocks, such as filters, baluns, couplers, dividers, matching circuits, are indispensible parts for RF frontend modules in cellular, WiFi, and WiMAX applications. As form-factor is a critical requirement for mobile devices, smaller-size IPDs have been showing advantages and attractions. For a typical function, such as a filter, silicon substrate-based approach may achieve 5% size reduction, compared to a LTCC approach. In addition, the thickness of the IPD is typically in 15. um to 25. um ranges, which is much thinner than using LTCC approaches, and therefore is very suitable for SiP applications. These smaller form-factor and lower profile features do not come without any price. As the volume size is reduced in IPD, the quality-factor Q of an inductor, in Figure 6: IPDs with wire-bonding pads. Top: GSM low-pass-filter with coupler, 1.4 mm x 1.2 mm. Bottom: WiMAX filter with balun function, 1.6 mm x 1.2 mm. Some IPD examples for wirebonding configuration, and for flip-chip application, are shown in Figure 6 and Figure 7, respectively. For RF applications, models for bonding wires have to be carefully evaluated or verified for designs, as inductance-only models may not predict their behaviors well, especially for higher frequency applications (e.g., for 6. GHz or above). Sometimes, models taking into account of mutual coupling of wires are also needed. 881

5 the PCB. The amplitude-imbalance of this device is less than.4 db, and the phaseimbalance is less than 5. degree, with respective to 18. degree. The differential mode insertion-loss is -2.6 db, and the return-loss is better -15. db. Rejection of cellular signals (at < 2GHz) is better than 3. db. Figure 7: IPDs with bumps for flip-chip applications. Top: GSM balun, 1.4 mm x 1.2 mm. bottom: UWB filter, 1.6 mm x 1.2 mm. A measured response of a wirebondable IPD working in 3.3 GHz to 3.9 GHz (balanced filter) is depicted in Figure 8. The device was wire-bonded to a test board with a short 5. Ohm line for each port. The measured data includes the contribution from the wires and the 5. Ohm traces on SYSTEM-IN-PACKAGE MCM (multiple-chip-module) using QFN are probably the most efficient packages for RF applications. Figure 9 shows a design layout (bond diagram) for a RF QFN package. Three chips (IPD being one chip) are placed side by side in the package. All the interconnections are made by the bonding wires. For RF devices to work properly, accurate wire models (not only wire inductance) should be used during design phases. These models should include mutual inductance and mutual capacitance impacts. Insertion Loss (db) Amplitude Imbalance (db) Return Loss (db) Phase Imbalance (deg Figure 8: Measured response for the IPD shown in the lower side in Figure 6. The IPD was bond-wired to a test board on which the measurement was taken. 882

6 For a low-pass-filter IPD in wirebonding configuration, the grounding wires (sometimes called down bonding in QFN packages) would have noticeable impact on harmonic attenuation levels. It is preferred that the wires are short, or as short as possible. In the wire-bonding technology, there is a clearance on these down-bonding wires. As a result, there is a lower limit on the grounding inductance. To make the grounding inductance tunable for fast development, pads for multiple-wires, as shown in the left in Figure 1, can be used. This allows to implementing different downbonding configurations, in order to meet stringent harmonic attenuation requirements. Figure 1: Two low-pass-filter designs for MCM packages. Design #1 at the left:.69 mm x.82 mm. Multiple-wire pad for down bonding. Design #2 at the right:.82 mm x.56 mm. Single-wire pad for down bonding. m4 freq= 2.5GHz db(s(1,2))= m5 freq= 5.GHz db(s(1,2))= m6 freq= 7.2GHz db(s(1,2))= S-Parameter (db) m4 m5 m E9 4.E9 6.E9 8.E9 1.E1 Freq Figure 11: Typical response of design #1 as shown in the left figure in Figure 1. Figure 9: IPD used in a MCM QFN package. A high-attenuation low-pass-filter design for WiFi applications is shown in Figure 11. This IPD has very small formfactor (.69 mm x.82 mm x.15 mm), with over 3. db attenuations at harmonic frequencies. This electrical performance is equivalent to that from LTCC approaches, but the IPD is much thinner (or as thin as other active chips to be in a package), and may be used in SiP efficiently. Besides IPDs used as individual components for MCM or SiP, several functional blocks (filter, balun, matching, etc.) may be made in one big IPD tile, which also serves as a building substrate with routing, for assembling some active dies onto it. Figure 12 shows a design example of chip-scale module packages, where two chips are to be bonded (using flip-chip) on a big IPD tile. In this IPD tile, there are some passive functions embedded in the silicon substrate. In addition, all the routing is 883

7 through the IPD tile and finally connected to the second-level interconnection balls at the periphery. As components (chips, passives, routing and interconnections) can be implemented in smaller areas through wafer process, a completed chip-scale package may be much smaller than realized using other approaches (e.g., LTCC or laminate substrates). Typically 3% - 4% size reduction may be achieved. Figure 12: Chip scale module package. The response of the passive functional blocks embedded in the IPD tile could be different, to some extent, from those of IPDs used as stand-alone components for MCM or SiP. To characterize the response of the passive circuits embedded in the big IPD substrate, probing pads can be added in the engineering stages, as shown in Figure 13, which allows to correlate design approach, and to perform trouble-shooting. Figure 13: A chip-scale module package under probing. Not only bumps can be used for the second-level interconnection (in Figure 12), bonding-wires can be also used to connect with other parts in packages. Figure 14 illustrates a big IPD tile sitting on a flip-chip die (RFIC). In this package, the IPD tile is wire-bonded to a laminate substrate. Some active chip and discrete components can be mounted onto the IPD tile. In a stack-die package, there could be more interference between the top die and the bottom die, compared to them being placed side by side. The interference is mutual. The top die and the bottom die can be either aggressor or victim. For the RFIC to work properly, the interference from the IPD should be minimized. This may be resolved by designing the coils inside the IPD far enough from some critical parts in the RFIC (e.g., VCO) in lateral distance. Switch IPD RFIC Laminate Substrate SMD Figure 14: Chip-scale module used in stack-die BGA package. h2=15. um, h1=2. um, h=7. um. h2 h1 h 884

8 On the other hand, to ensure the passive functions in the IPD work properly in the presence of the bottom die, design should take into account of the actual stackup. In this case, the RFIC chip was made from CMOS substrate with 2. um (h1) thickness. The flip-chip bump has 7. um (h) bump stand-off height. The IPD in the stack has thickness of 15. um (h2). S-parameters S-parameters m1 freq= 2.5GHz db(s(1,2))= m1 m2 Differential Mode Single-end Return Loss -4 1.E9 2.E9 3.E9 4.E9 Freq m2 freq= 2.5GHz db(s(4,5))= E9 4.E9 6.E9 8.E9 1.E1 Freq Figure 15: Measured electrical responses for an IPD working at WiMAX band. Blue: from measurement on 15. um IPD wafer um CMOS wafer. Red: from measurement on 42. um IPD wafer. To characterize the IPD s performance in the actual stack-up configuration, two experiments were undertaken through wafer-probing. In one measurement, the IPD wafer was backgrinded to about 42. um (h + h1 + h2). In another measurement, the IPD wafer was back-grinded to about 15. um thickness, and then was stacked on to a bumped CMOS wafer with total height (h + h1) being about 27. um, to closely represent the actual stack-up package as shown in Figure 14. The IPD under test is a balanced filter working at 2.5 GHz band, with attenuation requirements of 3. db at cellular-phone bands and at its 2 nd and 3 rd harmonics. As can be seen in Figure 15, typically made CMOS chips (resistivity in Ohm-cm range) do not make considerable impact on the filter s insertionloss and return-loss. It can also be seen that the WiMAX IPD shows clean response with good insertion-loss and return-loss in passband, and high attenuation in stop-bands. REFERENCES [1] K. Liu and R. C. Frye, Full-Circuit Design Optimization of a RF Silicon Integrated Passive Device, in Proc 15 th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp , Oct. 26. [2] J. Mondal, et al. Design and Characterization of an Integrated Passive balun for Quad band GSM Application., in Proc. 56th Electron. Comp. Technol. Conf., 26, pp , June 26. [3] K. Liu, R. Frye, and R. Emigh, Bandpass-filter with balun function from IPD technology, in Proc. 58th Electron. Comp. Technol. Conf., 28, pp [4] C. H. Chen, et al, Very Compact Transformer-Coupled Balun-Integrated Bandpass Filter Using Integrated Passive Device Technology on Glass Substrate, In Proc. 21 International Microwave Symposium, pp

9 [5] W. G. El Dine, et al, Three Approaches for the Realization of a Chebyshev Cross- Coupled UWB Filter, In Proc. 21 International Microwave Symposium, pp [6] C. H. Chen, et al, Integrated Balun Band-pass Filter Design with an Optimal Common Mode Rejection Ratio, in Proc. 61th Electron. Comp. Technol. Conf., 211, pp

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