Trends in LED manufacturing: How to reduce LED cost of ownership SEMICON Taiwan 2012 Pascal Viaud - CTO

Transcription

1 Trends in LED manufacturing: How to reduce LED cost of ownership SEMICON Taiwan 2012 Pascal Viaud - CTO Verticle Inc Lumileds OSRAM Aixtron CREE OSRAM OSRAM Cascade Microtec 75 cours Emile Zola, F Lyon-Villeurbanne, France Tel: Fax: Web:

2 Yole Développement in a nutshell Yole Developpement is a market, technology and strategy consulting company, founded in We are involved in the following areas: Photovoltaic Power Electronics Microfluidic & Med Tech Advanced Packaging HB LED, LED & LD Wafers and Substrates MEMS & Imaging sensors Our different activities: custom analysis (consulting), patents analysis, reverse engineering & reverse costing, reports publication, media business and Yole Finance services (M&A, due diligence, fund raising)

3 History LED Industry is Entering its 3 rd Growth Cycle August

4 Packaged LED Revenue Forecast by Application August Increase of penetration rate of LEDs 2 Decrease of aftermarket volume (replacement) due to higher lifetime of LEDs

5 SSL Upfront Cost: Sticker Shock*: <$1 $3-5 $20-$40 Need to reduce $/lumen! *All sources: 60 W equivalent ~ 800 lumens, warm White, tier 1 brand only, typical price in the US

6 The Path to Cost Reduction Manufacturing Cost: Cost = $$ Lumen Higher equipment throughput Higher yields Economy of scale Materials > 4x? LED performance: Higher Efficiency (lumen/w) More light / chip (driving current) 2-3x?

7 20 Key Technologies & Research Areas Relative Impact on LED cost of ownership Manufacturing Cost LED on Si Lithography: Dedicated tools, Higher Throughput Testing and Binning: Wafer Level, Higher throughputs Die Singulation Increased throughputs and yields Contacts/Electrodes: Transparent contacts/electrode materials and patterns Large Diameters Substrates: 4, 6, 8 Epitaxy: Cluster tools - New Epi Technologies Substrate Separation: Laser Lift Off, other separation techniques Encapsulation Materials and Optics: Ageing and optical properties Contacts & Electrodes: p to n layer VIAS Wafer Level Packaging: Silicon TSC, Wafer Level Optics Phosphors: Conversion efficiency, Color Rendering IP free phosphors Mirrors: Resonant Cavities Mirrors: Improve reflectivity/electrical properties Surface Texturation: Patterned substrates / Roughening Epitaxy MOCVD: Higher yields and Throughputs - Improved Material quality Phosphors: Quantum dots Phosphors Other Alternative substrates: GaN, ZnO,Engineered substrates Thermal Management: New materials for packaging Surface Texturation: Photonic and Quasi Photonic Crystals Current Droop / Green Gap / LED Structures Sources: Yole Développement LED Performance

8 Luminaire Cost Structure LED is only one contributor but represents the single largest opportunity for cost reduction: LED Component 45% Downlight picture: CREE LR6, Cost breakdown from DOE SSL roundtable 2011, Packaged LED pictures: Cree, Everlight, Osram, Philips Lumileds

9 Substrates: larger, patterned, 2 to 6 : better use of reactor real estate (Aixtron) Better use of reactor real estate + reduced edge losses = 15 to 65% throughput improvement. Downstream benefits on Lithography (full field): Cost / Wafer (with 5 mask levels) 2 6 $1 $1 Cost/TIE $1 $ Benefits of PSS for light extraction have been extensively demonstrated. PSS adoption is increasing fast, despite IP concerns. In million of TIE / y PSS Std. Substrates % PSS 21% 38% 79% 81%

10 Substrates: LED-on-Silicon? 99.5% of GaN HB LED currently made on Sapphire, SiC but If it can be made on Silicon, it will be made on Silicon Popular saying from the Semiconductor industry ~ 5-10% depending on type of LED Example of a high power 1W HB-LED cost structure (Source: Yole, System plus consulting) Si wafers are less expensive than sapphire Is this where the cost savings come from?

11 LED-on-Si: Potential Cost Benefits Assumptions: Identical yields 200 mm Silicon processed in fully depreciated CMOS fab - 60% at the die level? Benefit of Si would stem from switching to 8 and using fully depreciated & highly automated CMOS fabs

12 Is Silicon Taking Over (yet)? Silicon Sapphire, SiC?

13 LED-On-Si: Some Players: Most LED makers have LED on Si research programs: Osram, Samsung, Lumileds, Epistar Bridgelux + Toshiba committed to Si transition in Oct. 2012, Lattice Power already in production. Osram 6 LED Epiwafer Bridgelux 8 LED Epiwafer Lattice Power Led-On-Si chip

14 LED-On-Si: Potential Benefits CMOS processing Wafer Price Higher Thermal Conductivity Non Transparent Material Highly automated, efficient Large process toolbox Silicon is cheaper than sapphire and will likely remain so. (Sapphire = hard material + high melting point) Better Temperature Homogeneity More accurate Surface Temperature Measurement Low cost: 10x improvement vs. 2 sapphire (!?) New LED structures? Low wafer price 200 mm available But not semi standard (yet?) Improved Binning Yield? Improved Run/Run repeatability? Direct manufacturing cost Potential yield benefits

15 LED-On-Si: Main Challenges Lattice Mismatch Thermal Expansion Coefficient Mismatch Melt Back Blue Light Absorption by Wafer Impact Sapphire Epitaxial Defect Wafer Bow Inhomogeneity Layer Cracking Poor epitaxy Poor light output Bad Bad No No Worse Much worse Yes Yes Silicon

16 LED-On-Si: Conditions for Success #1: Must equal LED on Sapphire performance.? #2: Must reach similar manufacturing yields: the major issue.? #3: Must be compatible with CMOS, ideally on 200 mm wafers: some problems (gold contamination, testing, dicing )

17 Will LED-on-Si Happen?... It s a cost game: $/lumen rules. Si enables 200 mm in CMOS fabs Price declining (Yole Developpement) Sapphire/SiC = moving targets! Price, PSS 8 possible (?) If technology hurdles are cleared, LED- On-Si will be adopted by some LED manufacturers but not necessarily become the standard. Monocrystal

18 LED Manufacturing Yields 50% of LED chips going into the trash?

19 The Cost of Yields Bad dies have to be processed all the way through singulation... Front End Level 0: - - Epitaxy Front end Level 1: Back End Level 0: - Bonding - Lithography - Etching - Metallization Back End Level 0: - Epitaxial substrate removal Bad areas Defective die Back End Level 0: - Dicing Back End Level 0: - Testing and binning Pick and Place Bin #1 Bin #2 Bin #3 Bin #n Stretchable tape Defective & Rejected Dice and carry the same cost as good die!

20 Yields: MOCVD The single largest opportunity for HB LED cost reduction? Veeco Maxbright Cluster tools: 2 to 4 reactors for high capacity, throughput, footprint and capital efficiency. Aixtron G5HT 2 x 56 configuration Direct Saving (Yield + Throughput improvement) + Downstream savings!

21 MOCVD Cost of Ownership Trends Cost reduction will be achieved through a combination of increased reactor throughput, automation, better yields, improved reliability (uptime) and utilization of precursors. Aixtron: LED Epitaxy cost reduction roadmap

22 Dedicated Tools for LED: LED industry still using lots of old refurbished semiconductor tools Low yields / performance X Suss MA100/150e Gen2 Litho system Evaporator for ITO and metal LED deposition (SNTEK) Dry etching for PSS and GaN (Corial) EVG LED wafer bonder LED industry now large enough to justify development of dedicated tools!

23 Packages Designs Mid Power (1-2 die, typical dimension: 0.3 to 0.8 mm) Single Large Die (1 die, typical dimension: 0.5 to 1.5 mm) Multiple Large Dice (3 to 25 dice, typical dimension: 0.5 to 1.5 mm each) Small/medium COB Array (20 to 100 dice, typical dimension: 250 to 500 um each) Single or Multi Jumbo Die 1 to 6 dice, typical dimension 2 to 5 mm each) Lumileds Cree Luminus Device Cree Sharp Luminus Device Osram Osram Lumileds Osram Edison Opto Luminus Device

24 Standardization can reduce cost: Lighting applications require high power packages, right? Mid-power LED price decreased dramatically in 2011 under the combined effects of: Package standardization Very large volumes. High level of competition (over supply) 2 Chip 5630 packages (Seoul Semiconductor) Highly competitive $/lumen ratio Retrofit bulb Linear Lighting (Senslite Corporation) 5630 package for lighting (Philips Lumileds ) Mid power packages crossing over from display to lighting

25 System Design Choice Design choice are often application dependant. But in some cases, multiple designs and choice of package are possible for a single application: Package design can improve yield and reduce LED cost of ownership

26 Conclusion: The Path to Cost Reduction System approach: Chips performance impacts package cost of ownership. Package design impacts chip yields. Equipment: Tools designed specifically for LED manufacturing offer improved throughputs and cost of ownership. Substrates: Larger wafers, LED-On-Si have potential but still yield/technology limitations. And Sapphire performance are improving (PSS). Manufacturing Philosophy Semiconductor Best Practices now entering LED industry: automation, cassette/cassette, MES

27 THANK YOU! Please visit our booth #1327 Contacts Asia: Taiwan/China: Mei-Ling TSAI Korea: Hailey YANG Japan: Yutaka KATANO