A Dynamic Releasing Scheme for Wafer Fabrication

Transcription

1 A Dynamic Scheme for Wafer Fabrication A Dynamic Scheme for Wafer Fabrication 1 Yu-Hsin Lin, 2* Chih-Hung Tsai, 3 Ching-En Lee and 3 Sheng-Kaung Liu 1 Department of Industrial Engineering and Management Ming-Hsin University of Science & Technology 2 Department of Industrial Engineering and Management Ta-Hwa Institute of Technology Hsin-Chu, Taiwan, ROC ietch@thit.edu.tw 3 Semiconductor Manufacturing Management Center National Chiao-Tung University Abstract This paper presents a dynamic releasing scheme (D-Roll), which determines when and which wafer lot should be released into the shop floor using the concept of rolling correction. With real-time information from manufacturing execution system (MES), the priority and the time point of releasing can be adjusted dynamically. The performance measures used in this paper are throughput, cycle time, WIP (Work-In-Process), turn-rate, delivery, and bottleneck utilization. The results show that the proposed dynamic releasing scheme is better than other conventional strategies (WIP to bottleneck control, starvation avoidance, fixed-wip, and uniform loading). Keywords: Wafer Fabrication, Dynamic, Manufacturing Execution System 1. Introduction Scheduling in semiconductor manufacturing is perhaps one of the most difficult scheduling tasks in the world. Wafers undergo hundreds of different processing steps and often return to the same workstation repeatedly. When a machine fails, its repair time is unpredictable. Besides, the fabrication process is subject to random yield crashes, so some wafers need to be reworked occasionally. Due to the recession of semiconductor industry since 1996, customer service becomes more and more important in wafer foundries. To improve custom service, uncertainty of product mix may also increase. All these variabilities make the scheduling and dispatching decision even harder. With the continuous improvement of computer-integrated manufacturing (CIM) systems in Wafer fabrication, the computing speed and the ability of production planning and control is getting better and better. Real-time decisions based on global factory status can be made. Because releasing plays an important role of improving production indices such as, throughput, cycle time, delivery, and so on (Wein, 1988; Graves et al., 1995; Sabuncuoglu and Karapinar, 1999), developing a dynamic releasing scheme in wafer fabrication is necessary and doable nowadays. Most previous studies (Glassey and Resende, 1988; Goldratt, 1990; Yan et al., 1992) focused on the determination of when International Journal of The Computer, the Internet and Management Vol. 15#1 (January April, 2007) pp

2 Yu-Hsin Lin, Chih-Hung Tsai, Ching-En Lee and Sheng-Kaung Liu a wafer lot can be released into the shop based on the status of a given bottleneck. However, in wafer fabrication, the bottleneck is usually changing dynamically. How to determine which workstation is the bottleneck is an important issue. Additionally, how to synthesize uncertain factors (e.g. product mix), unscheduled events (e.g. machine failure), due dates, and machine and wafer characteristics to develop a dynamic releasing scheme is an essential and worthwhile study. Therefore, the objective of this research is to develop a dynamic releasing scheme for wafer fabrication using the rolling correction concept. Bottleneck starvation avoidance, line balance, lot grades, due dates, and shop floor information are factors to be considered in the proposed releasing scheme. Which lot at what time to be released to the fab has to be determined through the dynamic releasing scheme. In this paper, the performance measures are cycle time, throughput, WIP, turn-rate, delivery and bottleneck utilization. 2. Methodology Many releasing policies for wafer fabrication have been proposed in recent years (Glassey and Resende, 1988; Lozinski and Glassey, 1988; Wein, 1988; Leachman et al., 1988; Lou and Kager, 1989; Goldratt, 1990; Spearman and Woodruff, 1990; Yan et al., 1992; Lee, 1995; Chen, 1996). In general, all these releasing strategies make either one or both of the two decisions: (1) what is the releasing priority of wafer lots and (2) when to release a specific wafer lot. The strategy in determining the releasing priority can be either static or dynamic. Dynamic releasing strategies consider shop floor information and making releasing priority decision dynamically while static ones do not. 2.1 The External Information and Dynamic Scheme To understand the function of the dynamic releasing scheme, the information in and out of the dynamic releasing scheme must be clarified first. A well-known wafer foundry in the Science-Based Industrial Park in Taiwan is studied in this paper. Manufacturing department is responsible for detailed scheduling (releasing and dispatching) as well as shop floor monitoring and control. In some special circumstances such as capacity loss due to scrape or rework, manufacturing department may send a special command or change request to the dynamic releasing scheme. Production control department is responsible for MPS (Master Production Scheduling) and Fab-wide scheduling. Production control department regularly checks with manufacturing department and determines the releasing amount of a planning period (4 days) to fulfill the MPS. Engineering department is responsible for analysis, design, and experiment new technology. Therefore, engineering lots with higher priority may be released to the fab indefinitely and they will interrupt pre-specified schedule. In addition, real time shop floor information such as WIP status and turn-rate must also be sent to the dynamic releasing scheme. By synthesizing all these information, the releasing scheme can make an ultimate releasing decision. Figure 1 shows the basic information requirements for the releasing scheme. The middle of Figure 1 shows the detailed functional modules of the proposed dynamic releasing scheme. The bottleneck identification module identifies the bottleneck as well as the corresponding first bottleneck stage for each 4-day planning period. Each wafer lot may visit the bottleneck several times due to the reentrant characteristic. The stage that each wafer lot 34

3 A Dynamic Scheme for Wafer Fabrication visits the bottleneck at the first time is defined as the first bottleneck stage (see Figure 2). Because the first 10 operation stages from wafer start are common stages for all types of wafer lots in the studied wafer foundry and because these operation stages cover almost all front-end processing machine groups, it is assumed that the first bottleneck stage of each wafer lot is identical in this research without loss any generality. The priority evaluation module evaluates the lot priority and gives each wafer lot a priority index score. The real-time releasing module decides which lot can be released into the fab at the releasing point of time. The releasing menu lists all wafer lots to be released in every 4-day planning period provided by production control, manufacturing, and engineering departments. Normal lot, hot lot defined by PC department Special releasing command defined by manufacturing department Pilot/engineering lot defined by engineering department Normal and hot lot information Special releasing command Feedback of releasing command menu Engineering lot information Turn-rate information Manufacturing Execution System (MES) command Priority evaluation module priority of each wafer lot menu information Dynamic Scheme WIP status information Real-time releasing module Bottleneck identification module Bottleneck Note: : Module : Data file Data flow Figure 1: The dynamic releasing scheme and its external information Bottleneck machine group Wafer Start First bottleneck stage Note: i : Stage i of a specific route of a wafer lot Figure 2: First bottleneck stage International Journal of The Computer, the Internet and Management Vol. 15#1 (January April, 2007) pp

4 Yu-Hsin Lin, Chih-Hung Tsai, Ching-En Lee and Sheng-Kaung Liu 2.2 The Bottleneck Identification Module Bottleneck controls the throughput of the entire system (Goldratt, 1990). Therefore, the first module of the releasing procedure of the dynamic releasing scheme is to identify the bottleneck as well as the first bottleneck stage. The inevitable change of product mix results in the uncertainty of bottleneck. The unexpected event in shop is another factor that causes bottleneck shifting. The regular checking and identification of bottleneck is necessary. In this paper, the bottleneck is checked every 4 days which is the planning period and the empirical value currently implemented in the studied wafer fab. Within the planning period, the bottleneck will not shift often in its historical data since production control department determines product mix and releasing amount of wafer lots every 4 days to meet MPS in the studied fab. The bottleneck in the planning period can be predicted using equation (1). I = N H - ( X ij R ij ) (1) i j where H : working hours per period. i : product type. I : total machine idle time in a planning period (4 days). j : the number of visits. N : the number of machines in a machine group. R ij : the average processing time of product i at its jth visit to the machine group. X ij : the amount of wafer lots of product i at the jth visit to the machine group in the period. Equation (1) expresses the relationship between the capacity of the machine group in hours of work and the load placed on it per period. The bottleneck machine group is the machine group with the smallest idle time based on equation (1). The juncture of releasing depends on the WIP level in front of the first bottleneck stage. The decision of the juncture of releasing will be discussed in next subsection. 2.3 The Priority Evaluation Module Figure 3 shows the priority evaluation module. Lot releasing priority is determined in this module and is re-evaluated every three hours to reflect the change of the shop status. This is the so-call rolling correction. The function of this module is to set the priority of each wafer lot. Hot lot s priority is always higher than normal lot s priority one. When wafer lots are at the same grade, the higher priority index score the wafer lot owns, the higher its priority is. The priority index score is calculated by equation (2). The turn-rate index score is calculated by equation (3) according to the turn-rate of each product. When a machine is down or a machine s capacity is insufficient, the turn-rates of these products processed by that machine will drop. Therefore, the priority to release these corresponding affected wafer lots will be lowered. The higher turn-rate the product owns, the higher the corresponding wafer lots turn-rate index score is. In addition, the urgent index score is calculated according to the scheduled releasing date of each wafer lot on the releasing menu. The predetermined releasing date of each wafer lot is confirmed by production control, engineering, and manufacturing departments and recorded on the releasing menu. The earlier releasing date the wafer lot possesses, the higher its UI j is. S ij = W tr TR i + W ui UI j (2) where S ij : the priority index score of a wafer lot of product i on day j on the releasing menu. TR i : the turn-rate index score of product i. 36

5 A Dynamic Scheme for Wafer Fabrication UI j : the urgent index of a wafer lot on day j on the releasing menu. W tr : the weight of turn-rate index score. W ui : the weight of urgent index score. TR i = ( SM ik ) / WIP i (3) k where SM ik : stage moves of wafer lot k of product i every three hours. WIP i : average WIP of product i within that three hours. 2.4 The Real-time Module The function of the real-time releasing module is to provide releasing command to MES. Figure 4 shows the data flow chart of real-time releasing module. The system s WIP level affects both the cycle time and the throughput (Miller, 1990). There exist inherent conflict in the determination of a proper WIP level when attempting to both maximize throughput and minimize cycle time. Therefore, keeping adequate (not too high and not too low) inventory in front of bottleneck is important. To avoid the starvation of the first bottleneck stage, enough WIP between wafer start and the first bottleneck stage is required. Therefore, the rule for real-time releasing is that if W R <= S, then release the lot with the highest priority, where W is WIP between wafer start and the first bottleneck stage, R is the average cycle time of a wafer lot at the first bottleneck stage, and S is average processing time between wafer start and the first bottleneck stage, which is continuously updated in simulation. MES Turn-rate of each product within every 3-hour rolling period Calculate turn-rate index score of each wafer lot turn-rate index score Priority Module menu Calculate balance index score of each wafer lot Priority index score = W tr Turn-rate index score + W bi Balance index score Priority index score of each wafer lot Select the priority of each wafer lot balance index score Lot grade information Priority of each wafer lot Real-time releasing module : Process : Data flow : Input point : Output point Figure 3: The priority evaluation module International Journal of The Computer, the Internet and Management Vol. 15#1 (January April, 2007) pp

6 Yu-Hsin Lin, Chih-Hung Tsai, Ching-En Lee and Sheng-Kaung Liu MES Dynamic Bottleneck Module WIP status It is not releasing juncture Dynamic bottlenec Continuous checking of the releasing juncture (if W R <= S?) It is releasing Real-time Module Select the lot with the highest priority index score in the releasing menu lot command Priority of each wafer Priority Evaluation Module MES : : Data flow : Input point : Output point Figure 4: The real-time releasing module 3. Numerical Example To demonstrate the effectiveness of the proposed dynamic releasing scheme, a numerical example and the corresponding simulation experiments are studied. The data of the numerical example is simplified and revised from the raw data provided by a well-known wafer foundry in the Science-Based Industrial Park in Taiwan. 3.1 Simulation Experiment In the numerical example, there are 11 machine groups including 98 machines. Two kinds of machine characteristics are considered. One is batch-type machine and the other is sequential-type machine. The processing time is conformed to Normal distribution. There are 4 product types in this environment, due to the variability of product mix in the wafer foundry, the product mix of the numerical example is assumed to be altered randomly per period. The due date of a specific wafer lot is set depending on its total raw processing time and its lot grade. That is, a hot lot has a more urgent due date setting than normal lot does (3 times of total raw processing time for a hot lot and 5 times of total raw processing time for a normal lot). There is a random machine down every 2,000 minutes. The 38

7 A Dynamic Scheme for Wafer Fabrication repair time is uniformly distributed between 360 and 2,160 minutes. The simulation time is 400,000 minutes for each run and a warm-up period is 100,000 minutes. Thirty runs with common random number streams are executed for each scenario. The performance measures were averaged over all replications, and the coefficient of confidence is 95%. 3.2 The Result Analysis In this paper, four conventional releasing strategies, fixed-wip (FW), uniform loading (UL), WIP to bottleneck control (WB), starvation avoidance (SA), are compared with the proposed dynamic rolling releasing scheme (D-Roll). The results are shown in Table 1 to Table 6. Among all four conventional releasing strategies, the releasing according to the bottleneck is the best. Wafer lots arriving just in time to be processed on the bottleneck result in better performance. It can be found that SA and WB are better than FW and UL on the performance measures of cycle time, WIP, turn-rate, delivery and utilization. Furthermore, SA is better than WB on cycle time, turn-rate, WIP, and delivery. This result indicates that WIP to be calculated based on time is better than based on quantity. Although D-Roll and SA are both in the best Duncan s group on most performance measures, D-Roll shows better digits than SA on all performance measures. Especially, D-Roll is significantly better than SA on throughput and bottleneck utilization measures. In addition, D-Roll outperforms WB, FW, and UL on all performance measures except that D-Roll and WB are not significantly different on utilization. Among these five releasing strategies, UL and FW give the poorest performance. In general, D-Roll is the best releasing strategies among these five. It shows the effectiveness of the proposed dynamic releasing scheme in this paper. Table 1: Throughput comparisons among of different strategies Strategy Mean ( lots ) Standard Deviation ( lots ) Duncan Grouping D-Roll 4, A WB 4, B SA 4, B C UL 4, C FW 4, C Table 2: Cycle time comparisons among of different strategies Strategy Mean ( minutes ) Standard Deviation ( minutes ) Duncan Grouping FW 7, A UL 7, A WB 6, B SA 6, C D-Roll 6, C International Journal of The Computer, the Internet and Management Vol. 15#1 (January April, 2007) pp

8 Yu-Hsin Lin, Chih-Hung Tsai, Ching-En Lee and Sheng-Kaung Liu Table 3: Turn-rate comparisons among of different strategies Strategy Mean ( stages ) Standard Deviation ( stages ) Duncan Grouping D-Roll A SA A WB B UL C FW C Table 4: WIP comparisons among of different strategies Strategy Mean ( lots ) Standard Deviation Duncan Grouping ( lots ) FW A UL A WB B SA C D-Roll C Table 5: Delivery comparisons among of different strategies Strategy Mean (%) Standard Deviation (%) Duncan Grouping D-Roll A SA A WB B UL C FW D Table 6: Bottleneck utilization comparisons among of different strategies Strategy Mean (%) Standard Deviation (%) Duncan Grouping D-Roll A WB A B SA B FW C UL C 40

9 A Dynamic Scheme for Wafer Fabrication 4. Conclusions This paper constructs a dynamic releasing scheme with the rolling correction concept and compare the proposed dynamic releasing scheme, D-Roll, with four other widely used conventional releasing strategies (FW, UL, WB, and SA). The results indicate that the priority index with an appropriate defined weights of urgent index and turn-rate index in determining lot priority is significantly helpful in increasing throughput while no significantly negative impact on other performance measures. Furthermore, D-Roll are significantly better than WB, FW, and UL on all performance measures except that D-Roll and WB are in the same Duncan s group on bottleneck utilization. Among these five strategies, D-Roll and SA are both in the same Duncan s group on most performance measures. However, D-Roll outperforms SA on throughput and bottleneck utilization and shows better digits than SA on other performance measures. The results demonstrate the superiority of D-Roll proposed in this paper. References [1] Chen, I.Z. (1996). Dispatching Rule for Semiconductor Manufacturing Based on Simulation. Master Thesis, National Tsing-Hua University, Hsin-Chu, Taiwan, R.O.C. [2] Chiou, W.H. (1997). A study of Dispatching Procedure for The Photolithography Area. Master Thesis, National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C. [3] Glassey, C.R. and Resende, M.G.C. (1988). Closed-loop Job Release Control for VLSI Circuit Manufacturing. IEEE Transactions on Semiconductor Manufacturing, 1(1), [4] Goldratt, E.M. (1990). The Haystack Syndrome. Croton-on-Hudson, North River Press, NY. [5] Graves, R.J., Konopka, J.M. and Milne, R.J. (1995). Literature review of material flow control mechanisms. Production Planning and Control, 6(5), [6] Hall, W.R. (1981). Driving the Productivity Machine: Production Planning and Control in Japan. Falls Church, American Production and Inventory Control Society, Virginia. [7] Leachman, R.C., Solozano, M. and Glassey, C.R. (1988). A Queue Management Policy for the Release of Factory Work Orders. ESRC Report , Engineering Systems Research Center, University of California, Berkeley, CA [8] Lee, K.J. (1995). The Construction of Production Planning System for Wafer Fabrication Factories. Master Thesis, National Chiao-Tung University, Hsin-Chu, Taiwan, R.O.C. [9] Lou, S. and Kager, P.W. (1989). A Robust Production Control Policy for VLSI Wafer Fabrication. IEEE Transactions on Semiconductor Manufacturing, 2(4), [10] Lozinski, C. and Glassey, C.R. (1988). Bottleneck Starvation Indicators for Shop Floor Control. IEEE Transactions on Semiconductor Manufacturing, 1(4), [11] Miller, D.J. (1990). Simulation of a semiconductor manufacturing line. Communications of the ACM, 33(10), International Journal of The Computer, the Internet and Management Vol. 15#1 (January April, 2007) pp

10 Yu-Hsin Lin, Chih-Hung Tsai, Ching-En Lee and Sheng-Kaung Liu [12] Sabuncuoglu, I. and Karapinar, H.Y. (1999). Analysis of order review/release problems in production systems. International Journal of Production Economics, 62, [13] Spearman, M.L. and Woodruff, D.L. (1990). CONWIP: a pull alternative to kanban. International Journal of Production Research, 28(5), [14] Wein, L.M. (1988). Schedule Semiconductor Wafer Fabrication. IEEE Transactions on Semiconductor Manufacturing, 1(3), [15] Yan, H., Lou, S., Gardel, S.S.A. and Deosthali, P. (1991). Using Simulation to Test the Robustness of Various Existing Production Control Policies. Proceedings of the 1991 Winter Simulation Conference,