EM681FV16B Family Low Power, 512Kx16 SRAM

Transcription

1 Document Title EM681FV16B Family 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Date Remark Initial Draft Oct Preliminary EM681FV16B(KGD), EM681FV16B series & EM681FV16BU series are unified to EM681FV16B Family. Apr Release -. VOH changed from 2.2v to 2.4v. -. Memory Function Guide updated in the last page tdw updated to 40ns. Dec Max added in the table of data retention characteristics Jul tdw updated in the WRITE CYCLE table in page 6 Mar Emerging Memory & Logic Solutions Inc. 3F Korea Construction Financial Cooperative B/D, Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : Tel : Fax : / Homepage : The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1

2 FEATURES Process Technology : 0.15μm Full CMOS Organization : 512K x 16 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min.) Three state output and TTL Compatible Package Type : 48-FPBGA, 44-TSOP2 GENERAL DESCRIPTION The EM681FV16B families are fabricated by EMLSI s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery backup operation with low data retention current. PRODUCT FAMILY Product Family Operating Temperature Vcc Range Speed Power Dissipation Standby (I SB1, Typ.) Operating (I CC1.Max.) PKG Type EM681FV16B KGD EM681FV16B - xx 1) LF EM681FV16BU - xx 1) LF Industrial (-40 ~ 85 o C) 2.7 ~ 3.6 V 45/55/70 ns 2 μa 2) 4 ma 48-FPBGA 44-TSOP2 1. xx represents speed. 2. Typical values are measured at Vcc=3.3V, T A =25 o C and not 100% tested. FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Row Select Memory Array 2048 x 4096 V CC V SS DQ8 ~ DQ15 DQ0 ~ DQ7 Data Cont Data Cont I/O Circuit Column Select A11 A12 A13 A14 A15 A16 A17 A18 WE OE UB LB CS Control Logic 2

3 PIN CONFIGURATIONS FPBGA-48 : Top view(ball down) 44 - TSOP2 : Top view A LB OE A0 A1 A2 NC B DQ8 UB A3 A4 CS DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D V SS DQ11 A17 A7 DQ3 V CC E V CC DQ12 NC A16 DQ4 V SS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE DQ7 H A18 A8 A9 A10 A11 NC A4 A3 A2 A1 A0 CS DQ0 DQ1 DQ2 DQ3 V CC V SS DQ4 DQ5 DQ6 DQ7 WE A18 A17 A16 A15 A TSOP A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 V SS V CC DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A12 A13 PIN DESCRIPTION Name Function Name Function CS Chip Select input V CC Power Supply OE Output Enable input V SS Ground WE Write Enable input UB Upper Byte (DQ8~DQ15) A0~A18 Address inputs LB Lower Byte (DQ0~DQ7) DQ0~DQ15 Data inputs/outputs NC No Connection 3

4 ABSOLUTE MAXIMUM RATINGS 1) EM681FV16B Family Parameter Symbol Ratings Unit Voltage on Any Pin Relative to Vss V IN, V OUT -0.2 to 4.0 V Voltage on Vcc supply relative to Vss V CC -0.2 to 4.0 V Power Dissipation P D 1.0 W Operating Temperature T A -40 to 85 o C 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS OE WE LB UB DQ0~7 DQ8~15 Mode Power H X X X X Deselected Stand by X X X H H Deselected Stand by L H H L X Output Disabled Active L H H X L Output Disabled Active L L H L H Data Out Lower Byte Read Active L L H H L Data Out Upper Byte Read Active L L H L L Data Out Data Out Word Read Active L X L L H Data In Lower Byte Write Active L X L H L Data In Upper Byte Write Active L X L L L Data In Data In Word Write Active NOTE : X means don t care. (Must be low or high state) 4

5 RECOMMENDED DC OPERATING CONDITIONS 1) EM681FV16B Family Parameter Symbol Min Typ Max Unit Supply voltage V CC V Ground V SS V Input high voltage V IH V CC ) V Input low voltage V IL ) V 1. TA= -40 to 85 o C, otherwise specified 2. Overshoot: V CC +2.0 V in case of pulse width < 20ns 3. Undershoot: -2.0 V in case of pulse width < 20ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f =1MHz, T A =25 o C) Item Symbol Test Condition Min Max Unit Input capacitance C IN V IN =0V - 8 pf Input/Ouput capacitance C IO V IO =0V - 10 pf 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current I LI V IN =V SS to V CC -1-1 μa Output leakage current I LO CS=V IH or OE=V IH or WE=V IL or LB=UB=V IH V IO =V SS to V CC -1-1 μa Operating power supply I CC I IO =0mA, CS=V IL, WE=V IH, V IN =V IH or V IL ma Average operating current I CC1 I CC2 Cycle time=1μs, 100% duty, I IO =0mA, CS<0.2V, LB<0.2V or/and UB<0.2V, V IN <0.2V or V IN >V CC -0.2V Cycle time = Min, I IO =0mA, 100% duty, CS=V IL, LB=V IL or/and UB=V IL, V IN =V IL or V IH ma 45ns ns ma 70ns Output low voltage V OL I OL = 2.1mA V Output high voltage V OH I OH = -1.0mA V Standby Current (TTL) I SB CS=V IH, Other inputs=v IH or V IL ma Standby Current (CMOS) I SB1 (Typ. condition : V CC 25 o C) CS>V CC -0.2V, Other inputs = 0~V CC (Max. condition : V CC 85 o C) LF - 2 1) 15 μa 1. Typical values are measured at Vcc=3.3V, T A =25 o C and not 100% tested. 5

6 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.4V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL 1) = 100pF+ 1 TTL(70nsec) CL 1) = 30pF + 1 TTL(45ns/55ns) 1. Including scope and Jig capacitance 2. R 1 =3070Ω, R 2 =3150Ω 3. V TM =2.8V 4. CL = 5pF + 1 TTL (measurement with t LZ, t HZ, t OLZ, t OHZ, t WHZ ) CL 1) V TM 3) R 1 2) R 2 2) READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40 o C to +85 o C) Parameter Symbol 45ns 55ns 70ns Min Max Min Max Min Max Unit Read cycle time t RC ns Address access time t AA ns Chip select to output t CO ns Output enable to valid output t OE ns UB, LB access time t BA ns Chip select to low-z output t LZ ns UB, LB enable to low-z output t BLZ ns Output enable to low-z output t OLZ ns Chip disable to high-z output t HZ ns UB, LB disable to how-z output t BHZ ns Output disable to high-z output t OHZ ns Output hold from address change t OH ns WRITE CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40 o C to +85 o C) Parameter Symbol 45ns 55ns 70ns Min Max Min Max Min Max Unit Write cycle time t WC ns Chip select to end of write t CW ns Address setup time t AS ns Address valid to end of write t AW ns UB, LB valid to end of write t BW ns Write pulse width t WP ns Write recovery time t WR ns Write to ouput high-z t WHZ ns Data to write time overlap t DW ns Data hold from write time t DH ns End write to output low-z t OW ns 6

7 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=V IL, WE=V IH, UB or/and LB = V IL ) Address t RC t OH t AA Data Out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE = V IH ) Address t RC t AA t OH CS t CO UB,LB t BA t HZ OE t OE t BHZ Data Out t OLZ Data Valid t OHZ t BLZ t LZ NOTES (READ CYCLE) 1. t HZ and t OHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection. 7

8 TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) Address t WC t CW (2) t WR (4) CS t AW UB,LB t BW t WP (1) WE t AS (3) t DW t DH Data in Data Valid t WHZ t OW Data out Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) Address t WC t AS (3) t CW (2) t WR (4) CS t AW UB,LB t BW t WP (1) WE Data in t DW Data Valid t DH Data out 8

9 TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) Address t WC CS t CW (2) t WR (4) t AW UB,LB t BW t AS (3) t WP (1) WE t DW t DH Data in Data Valid Data out NOTES (WRITE CYCLE) 1. A write occurs during the overlap(t WP ) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The t WP is measured from the beginning of write to the end of write. 2. t CW is measured from the CS going low to end of write. 3. t AS is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. t WR applied in case a write ends as CS or WE going high. 9

10 DATA RETENTION CHARACTERISTICS EM681FV16B Family Parameter Symbol Test Condition Min Typ Max Unit V CC for Data Retention V DR I SB1 Test Condition (Chip Disabled) 1) V Data Retention Current I DR V CC =1.5V, I SB1 Test Condition (Chip Disabled) 1) μa Chip Deselect to Data Retention Time t SDR See data retention wave form Operation Recovery Time t RDR t RC - - NOTES 1. See the I SB1 measurement condition of datasheet page 5. ns DATA RETENTION WAVE FORM t SDR Data Retention Mode t RDR V cc 2.7V 2.2V V DR CS, LB / UB GND CS > Vcc-0.2V 10

11 PACKAGE DIMENSION 44 - TSOP2 (0.8mm pin pitch) EM681FV16B Family Unit : millimeters / inches 11

12 48 Ball Fine Pitch BGA (0.75mm ball pitch) Unit: millimeters Top View B Bottom View B B1 0.5 A1 index Mark A #A1 C B C D E C1 C C1/2 F G H B/2 Side View 0.26 E2 D Detail A E E1 C Min Typ Max 0.79Typ Typ. A Y A B B C C D E E NOTES. 1. Bump counts : 48(8row x 6column) 2. Bump pitch : (x,y)=(0.75x0.75) (typ.) 3. All tolerence are +/ unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity : 0.08(Max) E Y

13 MEMORY FUNCTION GUIDE EMX XX XXX XX XX -XXXX EM681FV16B Family 1. EMLSI Memory 2. Device Type 11. Power 3. Density 10. Speed 4. Function 9. Package 5. Technology 8. Version 6. Operating Voltage 7. Organization 1. Memory Component 8. Version Blank Mother die 2. Device Type A nd generation Low Power SRAM B rd generation STRAM C th generation C CellularRAM D th generation E th generation 3. Density F th generation M G th generation M M 9. Package M Blank KGD, FBGA M S stsop M T TSOP M U TSOP M V SOP 4. Option 10. Speed Dual CS ns Single CS ns ns 5. Technology ns F Full CMOS ns ns 6. Operating Voltage ns T V ns V V U V 11. Power S V LL Low Low Power R V LF Low Low Power(Pb-free & Green) P V L Low Power S Standard Power 7. Organization X8 bit X16 bit X32 bit 13