Faculty of Manufacturing Engineering

Transcription

1 UNIVERSITI TEKNIKAL MALAYSIA MELAKA Faculty of Manufacturing Engineering WIP CONTROL AT END OF LINE OF SEMICONDUCTOR INDUSTRY USING CONWIP Lim Ke Sin Master of Science in Manufacturing Engineering 2014

2 WIP CONTROL AT END OF LINE OF SEMICONDUCTOR INDUSTRY USING CONWIP LIMKE SIN A thesis submitted in fulfillment of the requirements for the degree of Master of Science in Manufacturing Engineering Faculty of Manufacturing Engineering UNIVERSITI TEKNIKAL MALAYSIA MELAKA 2014

3 DECLARATION I declare that this thesis entitled "Wip Control At End Of Line Of Semiconductor Industry Using Conwip" is the result of my own research except as cited in the references. The thesis has not been accepted for any degree and is not concurrently submitted in candidature of any other degree. Signature... ~:.... Name Date Um ICE Sl/\J... 2 ~r ~ ''l.f

4 APPROVAL I hereby declare that I have read this dissertation/report and in my opinion this dissertation/report is sufficient in terms of scope and quality as a partial fulfillment of Master of Manufacturing Engineering (Industrial Engineering). : ~;~ ; Signature Supervisor Name... Date... :i-.j/ 7 j /;'I!...

5 DEDICATION To my beloved family members

6 ABSTRACT Advancement of technology and trends in globalization has resulted in higher customer demands and expectations. Manufacturers now offer mass customization to stay competitive. In the semiconductor industry, where product mix and volume are high, production is further complicated by the different process routes and processing times for different product families. Coupled with rapid changeovers of products, it is essential to keep the work in process (WIP) low in order to reduce the inventory level on the shop floor. Constant W1P (CONWIP) is a production control strategy applicable in many manufacturing environment that use cards to control W1P level. This research was conducted in a semiconductor manufacturing company facing difficulty in reducing the variation in WIP on the shopfloor. The objectives of this research are to design and develop simulation models for single loop CONWIP, multi loop CONW1P, hybrid CONW1P, single loop CONWlP and multi loop CONWIP with buffer size optimization based on the environment in the case company. With the developed models, the maximum throughput (TH) and minimum W1P were determined. Discrete event simulation models were developed using the Witness Software for processes at the End of Line (EOL) production in the company. Experiments were conducted using these models to compare the current system with the single loop, multi loop, and hybrid CONWIP control mechanisms. ln addition, buffer optimization incorporating single loop and multi loop control were also examined. Performance parameters of TH and WIP level were compared in all experiments. The results show that CONWTP production control is more effective in reducing WlP level compared to the current system. Secondly, the single loop CONWIP showed the least number of cards in the system. However, hybrid CONWIP is more robust and provides a better control mechanism compared to the single and multi loop system. Buffer optimization control can further reduce the number of cards in the single and multi loop control. The developed simulation models are useful to determine the number of cards in the system and buffer size for each process. With these models, the production personnel can monitor and control the WJP dynamically to meet current demands and utilize the shopfloor space for more productive purposes.

7 ACKNOWLEDGEMENTS Special thanks to my supervisor, Associate Professor Dr Chong Kuan Eng for his support throughout my research. Without his guidance and persistent help, this dissertation would not have been completed. I would like to express my appreciation for my family members and friends who supported and encouraged me throughout the time of this research. lll

8 DECLARATION APPROVAL DEDICATION ABSTRACT ABSTRAK ACKNOWLEDGEMENTS TABLE OF CONTENTS LIST OFT ABLES LIST OF FIGURES LIST OF APPENDICES LIST OF ABBREVIATIONS LIST OF PUBLICATIONS TABLE OF CONTENTS PAGE ii iii iv vi viii xi xiii xv CHAPTER 1. INTRODUCTION I. I Background 1.2 Background of the Study Manufacturing Process in Case Company EOL Manufacturing Processes 1.3 Problem Statement 1.4 Research Objectives 1.5 Research Scope 1.6 Significance of the Research l. 7 Organization of the Report 1 1 I LITERATURE REVIEW Introduction Work in Process (WlP) Pull System l WlP Management Job Release Policy l CONWfP CONWIP Control Strategies Applications of CONWIP Summary ofconwip Buffer Allocation Discrete Event Simulation (DES) I Simulation in Industrial Applications Summary RESEARCH METHODOLOGY Introduction Methodology Design - Process Flow, Problem Statement, Scope, Literature Review Model Development - Conceptual Model Model Development - Data Collection and Analysis Model Development- Verification and Validation Experimental Design of Experiment Run Experimental Design - Results, Discussion, Conclusion 64 IV

9 4. MODEL DEVELOPMENT AND EXPERIMENT AL DESIGN 4.1 Conceptual Model 4.2 Assumptions 4.3 Model Translation in WITNESS Software Modelling - Product Mix Distribution Modelling - Lot Size Modelling - Buffer Rule Modelling - Machine UPH Modelling - Machine Setup and Breakdown Modelling - Calculation of Cycle Time, Number of Lot Modelling - WIP Calculation 4.4 Model Verification and Validation 4.5 Designing the Experimentations Experiment I - Single Loop CONWJP Experiment 2 - Multi Loop CONWIP Experiment 3 - Hybrid Loop CONWJP Experiment 4 - Single Loop Buffer Optimization Experiment 5 - Multi Loop Buffer Optimization 5. RESULTS AND DISCUSSIONS 5.l Experiment I - Single Loop CONWIP Results 5.2 Experiment 2- Multi Loop CONWIP Results 5.3 Experiment 3 - Hybrid Loop CONWIP Results 5.3. l Results and Discussions of Single Loop, Multi Loop And Hybrid CONWIP with Optimizer 5.4 Experiment 4 - Single Loop Buffer Optimization Results 5.5 Experiment 5 - Multi Loop Buffer Optimization Results 5.6 Summary of Results and Discussions 5.7 Research Contributions CONCLUSION AND RECOMMENDATIONS 6.1 introduction 6.2 Research Conclusions 6.3 Limitations for Research 6.4 Recommendations for Future Research REFERENCES APPENDICES v

10 LIST OFT ABLES TABLE TITLE PAGE 2.1 CONWIP System Summary Experiment Factor and Response for the Simulation Study Model Scope Level of Details of Model Summary of Component List in the Simulation Model Product Mix Distribution Calculation Based on Case Company Historical Distribution of Lot Size in Case Company Based On Historical Data Attribute of Part in WITNESS Moulding Process UPH of 3 Leads UPH Mean, Standard Deviation and P-Value for Each Product Family Breakdown Time and Repair Time for Each Machine TH from the Simulation Model Product Percentage (Actual Data versus Simulation Data) Number of Production Cards Number of Production Card at Each Loop Single Loop CONWIP Results Multi Loops CONWIP Results Comparison of Base Model, Single Loop, and Multi Loop CONWlP Results 115 vi

11 TABLE TITLE PAGE 5.4 Hybrid CONWIP Results Sorted TH Level of Hybrid CONWIP Results Single Loop, Multi Loop, and Hybrid CONWLP Results Comparison Single Loop CONWLP Buffer Optimization Results Multi Loop CONWTP Buffer Optimization Results Comparison of Optimizer Results 135 VII

12 LIST OF FIGURES FIGURE TITLE PAGE l.l Major Processes in the Case Company EOL Process Flow in the Case Company 4 2. l Scheduling Dilemma (Nyhuis, 2006) CONWIP System. Movement of Parts Are Shown In Blue While Circulation of Release Authorizations in Green Tandem CONWIP Loops Coupled and Uncoupled CONWIP Loops Process Flow of the Project Framework for Conceptual Modelling Activity cycle diagram for Lot in the Factory Flow Chart of Lot in EOL Process Flow of Verification and Validation Logic Flow Diagram of Lot in EOL Single Loop CONWlP Flow Multi Loop CONWIP Flow Hybrid Loop CONWIP Flow Logic Flow Buffer Optimization Incorporates Single Loop CONWTP System l Logic Flow Buffer Optimization Incorporate Multi Loop CONWIP System Process Flow for Simulation Model The Input of Product Mix Distribution in Simulation Model Witness Simulation Initialize Actions Dialog 73 viii

13 FIGURE TITLE PAGE 4.3 Input Rule of Machine to Pull Product Detail Buffer of Op Mould Actions on Input for Buffer Op Mould Normality Test Result for Moulding Process for 3 Leads Descriptive Statistic and Power and Sample Size for 3 Leads Moulding Process Actions on Start Cycle for Machine Mould Setup Detail of Mould Machine Breakdown Detail of Mould Machine Actions On Output For Machine Count Simulation Modelling Program Flow Chart Simulation Base Model in WITNESS (a) Timeseries TH of the Simulation Model TH Normality Test Result for Simulation Model TH One Sample T-Test Result for Simulation Model I- Sample T-Test Result from Minitab Statistical Software CONWJP Control System Setting Number of Cards on Initialize Action lnput Rule for Planning Machine Processes of Multi Loop in CONWIP System Initialize Action Setting Number of Card Hybrid system at Input Rule of Machine Planning Model Optimization for Hybrid Loop CONWIP Model Optimization for Single Loop CONWlP Buffer Optimization Model Optimization for Multi Loop CONWIP Buffer Optimization WIP Level in the Single Loop CONWIP System TH versus WIP Level in the Single Loop CONWIP System Total WlP and Actual WlP in the Multi Loop CONWIP System TH Level in the Multi Loop CONWlP System WIP Level in Hybrid CONWlP TH level in Hybrid CONWlP 121 LX

14 FIGURE TITLE PAGE 5.7 Sorted TH level in Hybrid CONWIP 5.8 WIP Level for Single Loop, Multi Loop and Hybrid CONWIP 5.9 Buffers Size of Single Loop CONWIP Buffer Optimization Buffer Sizes of Single Loop CONWIP Buffer Optimization x

15 LIST OF APPENDICES APPENDIX TITLE PAGE Al WITNESS Documentor (Parts Entities) lss A2 WITNESS Documentor (Buffers Entities) 191 A3 WITNESS Documentor (Machines Entities) 19S A4 WITNESS Documentor (Transports Entities) 210 AS WITNESS Documentor (Attributes Entities) 213 A6 WITNESS Documentor (Variables Entities) 21S A7 WITNESS Documentor (Distributions Entities) 222 A8 WITNESS Documentor (Functions Entities) 226 Bl Moulding S lead 227 B2 Moulding 7 lead 228 B3 Tie Bar Cut 3 lead 229 B4 Tie Bar Cut 5 lead 231 BS Tie Bar Cut 7 lead 233 B6 Trim and Form Lead 3 23S B7 Trim and Form Lead S 236 B8 Trim and Form Lead B9 Auto Vision 3 Lead 238 BIO Auto Vision S Lead 239 xi

16 APPENDIX TITLE PAGE B 11 Auto Vision 7 Lead 240 B 12 Manual Inspection 241 CI Single Loop CONWIP Optimizer Results 242 C2 Multi Loop CONWIP Optimizer Results 243 D List of Components and Abbreviations in Simulation Model 244 E Product Process Routes 247 xii

17 LIST OF ABBREVIATIONS ACRONYM AHP AV BAP BAY BMould BPlate BPMC BTBC BTNF CAD CAPP CONLOAD CONWIP CT DES EDD EOL EVA FCFS FIFO FOL GA JIT MI DEFINITION Analytic hierarchy process Auto Vision Buffer allocation problem Buffer Auto Vision Buffer Moulding Buffer Plating Buffer Post Mould Curing Buffer Tie Bar Cut Buffer Trim and Form Computer Aided Design Computer Aided Process Planning Constant Load Constant WJP Cycle time Discrete Event Simulation Earliest due date End of line Economic value added First come first serve First in first out Front of line Genetic Algorithms Just in time Manual Inspection xiii

18 ACRONYM MOLD MSRD MTO MTS OBA PLATE PMC PO LC A QTMU SA SC SME SPC SPT STC TBC TH TNF TS UPH VMI WlP DEFINITION Moulding Multiple objective scheduling and real time dispactching Make to order Make to stock Optimal buffer allocation Plating Post Mould Curing Paired-cell Overlapping Loops of Cards Queue time maximum un-matches Simulated Annealing Supply chain Small Medium Enterprise Statiscal process control Short time processing Statiscal throughput control Tie Bar Cut Throughput Trim and Form Tabu Search Unit per hour Vendor managed inventory Work in process XIV

19 LIST OF PUBLICATION AND AW ARDS Lim, K.S., CONWIP Simulation Model for EOL Processes in Semiconductor lndustry. Malaysia Melaka Technical Universiti, Melaka, Malaysia, 22 February 2012, Won Silver Medal in UTeMeX Chong, K.E and Lim, K.S., CONWIP Based Control of a Semiconductor End of Line Assembly. Malaysian Technical Universities Conference on Engineering & Technology 2012, Perl is, Malaysia, November 2012, MUCET Chong, K.E and Lim, K.S., CONWTP Based Control of a Semiconductor End of Line Assembly. Procedia Engineering, vol.53, pp xv

20 CHAPTER 1 INTRODUCTION 1.1 Background In the highly competitive and globalized market, companies strive to ensure high levels of customers' satisfaction. On time delivery, qualities with minimum cost are the performance indicators that most customers emphasize on. At the same time, companies always try to maximize the utilization of the equipment, reduce lead time and unnecessary waste in order to increase the profit margin. In the lean manufacturing approach, inventory is one of the wastes and the most challenging part that exists in most companies. Semiconductor manufacturing involves complicated processes, routes, and parameters (Miyashita and Gautam, 20 I 0). Work in Process (WlP) is a critical issue for the semiconductor industry. WIP are parts that have been started but are not completed during the processes or sequence or routes within the factory. The accumulations ofwip and control policies are a challenge to the industry as holding or accumulation of WIP incurs cost to the company and often causes long process lead time. Proper WIP control and monitoring policies are critical to ensure that the company remains efficient and competitive. 1.2 Background of the Study In this research, the study will be conducted in a semiconductor company located at Batu Berendam, Malacca. The case company produces a variety of semiconductor products which include DRAMS, small signal devices, as well as power and logic devices. The 1

21 products are mainly supplied to the automotive manufacturers. There are 2 main categories of products namely the small package and the big package. The plant produces and final tests for the products Manufacturing Processes in Case Company The major manufacturing processes in the case company can be categorized into 3 groups which are front-of-line (FOL), end-of-line (EOL), testing and marking (TEST MARK) and, finally, quality check and packing processes as shown in figure I. I. die-bonding wire-bonding moulding plating trim-form testing+ marking ~ I front-of-line (FOL) end-of-line (EOL) testing + marking (TEST MARK) Figure 1.1: Major Processes in the Case Company FOL major processes which includes are the die bonding and wire bonding are take places in a clean room environment. The operators are enforced to wear full face cover uniform to avoid contamination of particle. In general, die bonding is a process assembly of a die from wafer which has been blade sawed into individual dies and attach to the package or a lead frame. For the wire bonding is a process of making interconnections between a die and package or lead frame of semiconductor devices assembly. The wires are to connect the bonding pad of each device to the lead frame which these wires generally made of gold, aluminium or copper. 2

22 EOL processes which also the important part that in this research including the major processes as moulding, electroplating and trim-form. ln later part of the chapter, will further expand the process which takes places. These processes are not conducted in a clean-room environment like FOL and involves with heavy machinery in the EOL module, as injection moulding machines, cutting and forming tools and electroplating machines. The moulding is the process of sealing a microchip die with a ceramic or plastic enclosure to prevent physical damage or corrosion. This is process take places after the wire-bonding has been completed at the FOL. Operators load and unload magazines which is a metal boxes that containing up to 40 lead frames to the moulding machine. Plating is the process for a surface-covering in the semiconductor industry. It is a method whereby the metals in ionic form are supplied with electrons to form a non-ionic coating (plate) on a desired substrate. For trim-form process consists in a moulded strip of components being loaded into a machine that cuts it into individual units called integrated chjps (lc). After trimmed, the same machine will perform "leg forming" where IC legs are bent, cut and formed into a desired shape. The third major processes of testing and marking processes, all the I Cs are tested I 00%with a machine. The test includes placing the IC in cold or hot temperature, and inducing electrical stress to test IC robustness and its functions. The markmg process is incorporated in a testing machine where good ICs will be marked with product information (product codes, date, logo, etc.) immediately after testing EOL manufacturing processes This study is conducted on the End of Line (EOL) manufacturing processes. As shown in Figure 1.2 the end of line actually involves 7 processes which include moulding 3

23 (MOULD), post mould curing (PMC), plating (Plate), manual inspection (MI), tie bar cut (TBC), trim and form (TNF) as well as auto vision (AV). The moulding process is to encapsulate the frame into the plastic form. The process of plating is completed by a subcontractor which outside the plant. On completion of the plating process, the lot will be sent back to the factory for manual inspection by an operator. Next, the lot will be sent for the tie bar cutting process and then the trim and form where all the units on the frame will be trimmed into pieces. Before the lots are sent for final testing, the lots will undergo the auto vision process which is an automated inspection process. Moulding Curing Tie Bar Cut Plating Manual Inspection Trim and Form Auto Vision Figure 1.2: EOL Process Flow in the Case Company. 1.3 Problem Statement The case company is a semiconductor manufacturer of high mix and high volume products. In one quarter of the production period, case company had produed lots with only one product family. This one product family carried 85 diferrent of products type which have different product routes and parameter. The processes are complex and the routes are different for each product which depends on the requirements or demands of the customers.. With average TH per day around 193 lots, the WlP in the system lies at around lots everyday. As the volumes are high, the production department monjtors the work stream to ensure that the WIP levels are within control. However, it is difficult to closely monitor the WlP level as the work streams are onjy updated at the end of every shift. Production engineer want to reduce the variation of WIP that float in the system so that the 4

24 WJP can be controlled at the satisfactory level. With lesser variation from the production floor, engineer can be response quickly when any problems occurs. Therefore, the company would like to determine a suitable way to control the WTP in the production lines. Jn addition, the company wants to identify the opportunities to reduce the cycle time and the waiting time of the lots inside the production. 1.4 Research Objectives In this research, the main aim is to investigate the WIP level using the CONWIP control mechanism based on the performance measures of maximum throughput (TH) and lowest WIP. The research objectives are: I. to design and develop simulation models for single loop CONWIP, multi loop CONWIP, hybrid CONWIP, single loop CONWTP and multi loop CONWIP with buffer size optimization based on the environment in the case company. 2. to determine the maximum TH and minimum WTP from each of the developed models. 1.5 Research Scope The scope of this research is limited to the EOL of the case company. One of the most frequent product family which consist 85 products will be taken into account to ensure that the simulation model represents the real environment. The key performance indicators for the research are WIP and throughput. The operational models for the proposed scenarios for different CONWIP control mechanisms are evaluated using the WITNESS simulation software with optimizer, while statistical analysis will be conducted with the Minitab Statistical Software. 5