Intel s Technology and Manufacturing Leadership. Brian Krzanich Senior Vice President General Manager, Manufacturing & Supply Chain Intel Corporation

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1 Intel s Technology and Manufacturing Leadership Brian Krzanich Senior Vice President General Manager, Manufacturing & Supply Chain Intel Corporation

2 Risk Factors Today s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q or 10-K filing for more information on the risk factors that could cause actual results to differ. If we use any non-gaap financial measures during the presentations, you will find on our website, intc.com, the required reconciliation to the most directly comparable GAAP financial measure.

3 Agenda Extending Intel s Technology Lead Intel s Manufacturing Advantage Intel s Capital Investment Philosophy

4 Predictable Silicon Track Record Executing to Moore s Law Enabling new devices with higher functionality & complexity while controlling power, cost, and size 180 nm nm nm nm nm nm nm 2011 Source: Intel

5 Leadership: The Right Choices at the Right Time Internal Research Broad Evaluation Tough Decisions Development Rapid Execution 1999: Copper Interconnect Skipped 180nm and aligned with mature equipment 200x: SOI Wafers Evaluated extensively, not worth the cost, >$500 million/ generation 2003: Low-k Interlayer Dielectric Chose CDO vs. SiLK 2003: Ge Strained Silicon Transistors Led the way with the right approach 2007: Immersion Lithography Skipped 45nm and saved >$400 million 2007: High-k Metal Gate Transistors Led the way with the right approach 2011: Tri-Gate Transistors The right path to fully depleted devices

6 Intel Introduces 3-D Tri-Gate Transistors at 22nm Gate Standard Traditional 2-D planar transistors form a conducting channel in the silicon region under the gate electrode when in the on state Tri-Gate 3-D Tri-Gate transistors form conducting channels on three sides of a vertical fin structure Gate Drain High-k Dielectric Source Drain Source Oxide Oxide Silicon Substrate Silicon Substrate Transistors Have Entered The Third Dimension

7 3-D Tri-Gate Transistor Benefits 37% performance increase at low voltage 50% power reduction at constant performance Adds only 2-3% wafer cost compared to 22nm planar Planar transistors can not provide expected performance and power improvements at 22nm The transition to 3-D Tri-Gate transistors continues the pace of technology advancement, fueling Moore s Law for years to come Source: Intel

8 Tri-Gate Innovation Extends Intel s Leadership nm 65nm 45nm 32nm 22nm Invented SiGe Strained Silicon 2 nd Gen. SiGe Strained Silicon Invented Gate-Last High-k Metal Gate 2 nd Gen. Gate-Last High-k Metal Gate First to Implement Tri-Gate Strained Si: > 3 years 1 st Competitor s Strained Si High K / Metal Gates: > 3 1/2 years 1 st Competitor s High K/MG Tri-Gate

9 Intel is Manufacturing Many Process Generations In High Volume 200mm 130nm 2001 Fab 17, Massachusetts 300mm 90nm 2003 Fab 24, Ireland 300mm 65nm 2005 Fab 12, Arizona Fab 24, Ireland Fab 68, China 300mm 45nm 2007 Fab 11X, New Mexico Fab 28, Israel 300mm 32nm 2009 D1C, Oregon Fab 32, Arizona Fab 11X, NM More Than Just Leading-Edge: We Support Most Technologies For 10+ Years

10 Faster Factories Enable Improved Customer Response Intel Cycle Time Cycle Time Benchmarking Data: Days Per Mask Layer Cycle Time Days Intel Other Semiconductor Manufacturers >60% Fab Cycle Time Reduction Intel s Cycle Time is Best in Class Sources: Intel and International Sematech Manufacturing Initiative (300mm Q4 2010)

11 Speed Makes A Difference 2009 Response 300mm Equivalent WSPW Source: Intel

12 Faster Time To Production Reduces Decision Lead Time 15% REDUCTION 31% REDUCTION 27% REDUCTION Construction TTP Fab Tool TTP Assembly/Test Tool TTP Days Days Source: Intel

13 Faster Ramps With Each Generation 22nm 32nm Wafer Starts 45nm 2H 11 Forecast 1H 12 Forecast Source: Intel

14 Supply Chain Agility Enabling Faster Delivery Beginning of 2009 Customer Forecast to Demand Demand to Wafer Starts Fab Transit Assembly/ Test Whse Ship Delivery Customer Dock End of 2010 Customer Dock ~40% Cycle Time Reduction Since 2009 Source: Intel

15 Agility in Action The Cougar Point Story Intel s Integrated Model Delivers Design Tools Process IDM Advantage Product Manufacturing Company-wide Coordination and Response Revised the Design Reallocated Manufacturing Capacity Reduced Logistics Cycle Time Micromanaged the Supply Line Increased Tool Performance Reduced Manufacturing Cycle Time Increased Output Masks Packaging Identified, Fixed, and Recovered Without a Revenue Impact Source: Intel

16 What Drives Capital Intensity? New Fabs Require More Capital and Earlier Spending 20 % Depreciation as a % of Revenues Four New Fabs Wafer Transition Two New Fabs One New Fab Two New Fabs One Fab Conversion 5 0 '98 '99 '00 '01 '02 '03 '04 '05 '06 '07 '08 '09 '10 '11 Forecast Source: Intel Depreciation in Line with Historical Levels

17 The Cost of a Leading Edge Fab Continues to Rise FAB $ 6.0 B PILOT LINE $ 1-2 B R&D PROCESS TEAM $ 0.5-1B The Cost to Build and Equip a New Leading Edge Fab Source: Intel

18 Fewer Companies Deliver Moore s Law Revenues from Shipments of Semiconductors Intel Samsung Electronics TSMC* Toshiba Renesas Texas Instruments ST Micro Hynix Micron Qualcomm Broadcom Infineon Elpida AMD Panasonic Freescale Sony UMC* NXP Marvell $ Billions Revenue To Support One Leading Edge Fab $12B revenue threshold** $9B revenue threshold** 2010 Estimates *TSMC and UMC are foundries.**theoretical estimate. Assumptions include 40% and 50% gross margins. Source: Company reports, IC Insights, Intel.

19 Advanced Process Technology Lowers Costs Ten Year Costs of Manufacturing and Process R & D $302B Same process for ten years Process R & D Manufacturing Costs $104B New process every two years Historical CAGR Unit Demand and Die Size with Transistor Growth Assumptions are theoretical and not forecasts. Source: Intel

20 Faster is Better Quarters per Process Technology Cycle (Beat Rate) 10 Year Mfg Costs Process R & D Costs are Lower with Shorter Process Cycles $17B $10B $4B Manufacturing costs grow faster than R & D costs Practical considerations limit reductions (staffing, retooling) Optimal cycle is eight quarters Theoretical analysis. Source: Intel

21 Capacity Deployed for The Long Term Capacity > Loadings? Capacity Loadings We manage the risk around long-term expectations Hypothetical 2015 Logic Capacity Wafer Starts per Week 300mm Equivalent Source: Intel

22 The Risk of Too Much Capital Spending What if: Growth in unit demand is half our forecast Intel has one more fab building than needed Equipment is already purchased for 22nm Contingency Plans: The building is mothballed for a year, to be used later 90% of the equipment fulfills 2012 requirements and will be used to reduce 2012 capital spending Cash risk: $125 - $175 Million for 22nm Opportunity: One Year of Full Production of a Leading Edge Facility (Billions) Source: Intel

23 Summary Extending Intel s Technology Lead Unprecedented power savings and performance gains Intel s Manufacturing Advantage Speed and Agility Make a Difference Intel s Capital Investment Philosophy Managed and Moderate Risk

24 Q&A

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26 Risk Factors The above statements and any others in this document that refer to plans and expectations for the fourth quarter, the year and the future are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, plans, believes, seeks, estimates, may, will, should, and their variations identify forwardlooking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forwardlooking statements. Many factors could affect Intel s actual results, and variances from Intel s current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be the important factors that could cause actual results to differ materially from the company s expectations. Demand could be different from Intel's expectations due to factors including changes in business and economic conditions, including supply constraints and other disruptions affecting customers; customer acceptance of Intel s and competitors products; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers. Uncertainty in global economic and financial conditions poses a risk that consumers and businesses may defer purchases in response to negative financial events, which could negatively affect product demand and other related matters. Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product demand that is highly variable and difficult to forecast. Revenue and the gross margin percentage are affected by the timing of Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricing pressures and Intel s response to such actions; and Intel s ability to respond quickly to technological developments and to incorporate new features into its products. Intel is in the process of transitioning to its next generation of products on 22nm process technology, and there could be execution and timing issues associated with these changes, including products defects and errata and lower than anticipated manufacturing yields. The gross margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; product mix and pricing; the timing and execution of the manufacturing ramp and associated costs; start-up costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; product manufacturing quality/yields; and impairments of long-lived assets, including manufacturing, assembly/test and intangible assets. Expenses, particularly certain marketing and compensation expenses, as well as restructuring and asset impairment charges, vary depending on the level of demand for Intel's products and the level of revenue and profits. The tax rate expectation is based on current tax law and current expected income. The tax rate may be affected by the jurisdictions in which profits are determined to be earned and taxed; changes in the estimates of credits, benefits and deductions; the resolution of issues arising from tax audits with various tax authorities, including payment of interest and penalties; and the ability to realize deferred tax assets. Gains or losses from equity securities and interest and other could vary from expectations depending on gains or losses on the sale, exchange, change in the fair value or impairments of debt and equity investments; interest rates; cash balances; and changes in fair value of derivative instruments. The majority of Intel s nonmarketable equity investment portfolio balance is concentrated in companies in the flash memory market segment, and declines in this market segment or changes in management s plans with respect to Intel s investments in this market segment could result in significant impairment charges, impacting restructuring charges as well as gains/losses on equity investments and interest and other. Intel's results could be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel s results could be affected by the timing of closing of acquisitions and divestitures. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. An unfavorable ruling could include monetary damages or an injunction prohibiting us from manufacturing or selling one or more products, precluding particular business practices, impacting Intel s ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. A detailed discussion of these and other factors that could affect Intel s results is included in Intel s SEC filings, including the report on Form 10-Q for the quarter ended October 1, Rev. 11/4/11