Designers Describe Next-Generation Application- Specific Devices

Transcription

1 End-User Analysis Designers Describe Next-Generation Application- Specific Devices Abstract: Systems designers rate third-party tool integration as one of the top factors in choosing an ASIC vendor, along with supplier track record and price, according to a Web-based Gartner Dataquest survey. By Bryan Lewis and Serena Hsu Strategic Demand Statements Designers want to work with suppliers that can offer cost-effective business models that can produce value-add high-functionality products and deliver fast time-to-market. Added value can come in many forms, including differentiated intellectual property (IP) and high levels of system integration. To win business, suppliers must have strong system knowledge and a successful track record in a vertical market. Publication Date:24 January 2003

2 2 Designers Describe Next-Generation Application-Specific Devices Study Objectives To move electronic systems closer to the goal of a single-chip solution, designers are asking more from application-specific integrated circuit (ASIC) and programmable logic device (PLD) vendors. More performance, more memory, more system library cores, more everything engineers are placing an increasing part of the system design task on their semiconductor partners. To quantify these requirements, Gartner Dataquest conducted a Webbased survey of system designers. This comprehensive study was designed to identify the current and future needs of the original equipment manufacturers (OEMs)/system suppliers as a guide for nextgeneration ASIC and PLD products. Highlights from the survey are presented in this End-User Analysis Perspective. More detailed information is available in the report "Designers Reveal Requirements for Next-Generation ASICs and FPGAs" (SCSI-WW-UW-0001). Methodology Gartner Dataquest recently completed the system designers User Wants and Needs report using a Web-based surveying system. End users are identified through a variety of means, including databases of past survey respondents and subscribers to engineering periodicals. More than 40,000 surveys were electronically distributed to sites around the world. We received close to 400 responses. Surveys were received and processed in the third and fourth quarters of. The data collected were predominantly from system design engineers and IC designers, who make up more than half of the respondents. The timing of the survey allows a comprehensive understanding of the state of the industry as well as future user requirements. Major Findings System designers revealed many interesting and important trends in the survey that will drive future requirements for ASIC, field programmable gate array (FPGA) and system on a chip (SOC) devices. Key findings include the following: Third-party tool integration is one of the top factors in choosing an ASIC vendor, along with supplier track record and price. Customer-owned tooling (COT) has begun to stall as we move into more complex devices using 130- and 90-nanometer process technology. Close to half of all ASIC designs today are system-level integration (SLI)/SOC, meaning that they have an on-chip compute engine such as a microprocessor core or digital signal processor (DSP) core.

3 Flash memory is gaining popularity over embedded dynamic randomaccess memory (DRAM). Close to 10 percent of today's cell-based integrated circuit (IC) designs have gate counts in excess of 10 million gates. More than one-fourth of PLD designers were doing designs of greater than 200,000 gates, with close to 20 percent working on designs of more than a half million gates. Package pin counts in ASICs and FPGAs are on a major rise, with 10 percent of cell-based IC designs in packages of more than 1,000 pins. Key Factors in Choosing an ASIC Vendor Figure 1 Key Factors in Choosing an ASIC Vendor To better understand how system designers go about choosing an ASIC vendor, Gartner Dataquest asked them to rate each factor in importance when selecting their ASIC vendors. Figure 1 illustrates the response. 3 Low NRE Charges Local Design Support Product Quality Advanced Technology Road Map Low Unit Prices Established Supplier Good Integration with Third-Party Tools Proven IP Cores Good Proprietary Tools Level of Importance Note: Ratings based on a scale of 1 to 7, in which 1= least important and 7 = most important It is interesting, and almost a given fact, that product quality tops the list in importance. Product quality can mean a number of things, including design quality and manufacturing quality. Good integration with thirdparty tools was a bit of a surprise in second place. Designers are saying that suppliers must invest in solid third-party support. The first two factors seem to be more of a must-have "check the box" factor, rather than a clear way for one supplier to differentiate from another.

4 4 Designers Describe Next-Generation Application-Specific Devices The ways for suppliers to differentiate and show true value lie in third place (established supplier), fourth place (low unit prices) and fifth place (proven IP cores). System companies want to work with suppliers that have a clear track record in their given vertical market that offers proven differentiated IP. Cost is always a way to differentiate, and customers like it, but is a last resort for chip suppliers, because this reduces profit margins. Interestingly, in these tough times, with design costs skyrocketing, designers did not seem overly concerned with the cost of nonrecurring engineering (NRE) charges. This is probably because NRE charges really do not vary that much from one vendor to another and are negotiable. Local design support is not a big deal for most, because important customers get their questions and concerns dealt with on site, and they do nothavetogotodesigncenters. Advanced technology road maps and good proprietary tools ranking so low on the list was a bit of a surprise. We expect to see them rise in importance as we move into the 90-nanometer-and-below design realm. Only a few companies, like IBM, really have R&D in place for tools and process to push the leading edge. COT vs. ASIC Model There has been a lot of talk in the industry about how the ASIC vendors may get pushed out in favor of customers doing their own designs using a COT flow, in which the customer does the entire design and takes it directly to the foundry. We wanted to measure this trend, so we asked system designers what business models they are using, and what they plan on doing in the future. Figure 2 shows the results from two different surveys with the same question. The first survey was done in late 2000, and the second was just concluded in late. The 2000 survey clearly shows an increasing interest in using a COT model, with about 21 percent using a COT model in 1999 growing to 24 percent in. Our most recent data for show that interest in moving to the COT model has tapered off in favor of the ASIC model. Our belief on why the COT model has tapered off and the ASIC model is coming back evolves around the increasing complexity of today's designs as we move to 0.13-micron and 90-nanometer designs. Many system companies are realizing that they must have a large in-house design team to get the entire design ready for the foundry. This becomes a large fixed cost that does not always get fully leveraged. Not only is this large fixed-design team costly, but also the risk associated with getting these designs to work is rising at a rapid rate. If the design does not work, the system companies take all the risk and miss the market window for their system. All of this leads to system companies realizing they should pay the ASIC company's premium for over-foundry pricing, because the fixed-design teams costs outweigh the extra costs of the ASIC vendor. ASIC vendors

5 5 also dramatically reduce the risk for the system companies, because they stand behind the design with a guarantee that the chip will work, or they will fix it quickly. Figure 2 ASIC Business Model (Percentage of ASIC designs) Percentage of ASIC Designs Traditional ASIC Design Services COT Increasing Complexity Device complexity is rapidly rising as more functionality gets consolidated in single-chip systems. To get a better measure of ASIC complexity, Gartner Dataquest has moved to counting total transistors, because this gives a more accurate measure when counting analog and memory. The conversion is four transistors equal a gate. The overall gate count trend is that gate arrays and FPGAs are used in lower gate counts, and cell-based ICs are used in higher gate counts. Figures 3 and 4 show the average transistor count for gate arrays and cellbased ICs, respectively. While the average cell-based IC transistor counts continue to climb above 20 million to 40 million transistors (5 million to 10 million gates), system designers are starting to use cell-based ICs with more than 120 million transistors (30 million gates). Maximum FPGA gate counts are clearly on the rise, too, as system designers start utilizing FPGAs with more than 500,000 gates (as shown in Figure 5).

6 6 Designers Describe Next-Generation Application-Specific Devices Figure 3 Gate Array Design Starts Average Transistor Count Transistors More Than 40,000,000 20,000,000-40,000,000 10,000,000-19,999,999 4,000,000-9,999,999 2,000,000-3,999, ,000-1,999, , , , ,999 Less Than 200,000 Percentage of Respondents Figure 4 Cell-Based IC Design Starts Average Transistor Count Transistors More Than 40,000,000 20,000,000-40,000,000 10,000,000-19,999,999 4,000,000-9,999,999 2,000,000-3,999, ,000-1,999, , , , ,999 Less Than 200,000 Percentage of Respondents

7 7 Figure 5 FPGA Design Starts Maximum Gate Count Gates More Than 500, , , , ,000 50, ,000 30,001-50,000 20,001-30,000 10,001-20,000 5,001-10,000 1,501-5, ,500 Percentage of Respondents ASIC Core Composition and Embedded Features With every new manufacturing process generation, maximum available gate counts dramatically increase, causing designers to search for new ways to use them. Increased use of IP cores and on-chip memory has been one of the prevailing trends over the past decade. Memory takes up about one-third of today's designs die area and is expected to grow to more than half within the next five years. Analog content is in high demand but seems to have stalled to some degree. Analog content is difficult to move on chip, because analog design tools have not been prevalent, and analog does not shrink as well as digital in the new manufacturing processes. New analog tools are entering the market to help incorporate on-chip analog. Figure 6 shows the percentage of cell-based IC die area taken up by each major type of function, according to our survey.

8 8 Designers Describe Next-Generation Application-Specific Devices Figure 6 Estimated Core Composition Cell-Based IC Design Starts Percentage of Die Area (I/Os Excluded) Random Logic Memory Analog IP Cores The demand for more on-chip memory is causing designers to explore new types of memory depending on speed or density requirements. Static random-access memory (SRAM) has been around for years and is clearly today's most popular type of memory. For years, there had been a lot of industry talk about using embedded DRAM for applications that require large blocks of memory. Many suppliers entered the embedded DRAM ASIC market over the past five years only to find that most designers were not willing to pay the premium over stand-alone DRAM. Stand-alone or off-chip DRAM pricing has taken some dramatic drops over the last five years, which also added to the problem. The net effect, the system designers are telling us, is that they see far fewer applications today than they did two years ago that will use embedded DRAM. Today's perceived embedded DRAM demand among the system designers that we polled had been cut in half from two years ago. Our survey two years ago also showed that perceived embedded DRAM demand was almost equal to that of nonvolatile/flash memory, but results from this year's survey show that flash demand is almost twice that of embedded DRAM. Figure 7 shows the perceived demand for each different type of memory, according to the current survey.

9 9 Figure 7 Perceived Demand for Embedded Memory Percentage of Respondents SRAM DRAM Rambus ROM Non-Volatile Gartner Dataquest Perspective As we peer into the future beyond the basic requirements by system designers, it is clear that the engagement model between suppliers and customers is evolving. Customers are exploring ways to reduce design and chip cost, because cost is king. ASIC suppliers must form an even tighter relationship with all their customers and partners as we transition to 90 nanometer, because this transition will be complex and difficult. Customers have stated their wants and needs, and it is time for suppliers to act. The / technology slowdown has changed the landscape, and no one can afford to just plod along the same path.

10 10 Designers Describe Next-Generation Application-Specific Devices This document has been published to the following Marketplace codes: SEMC-WW-DP-0235 For More Information... In North America and Latin America: In Europe, the Middle East and Africa: In Asia/Pacific: In Japan: Worldwide via gartner.com: Entire contents 2003 Gartner, Inc. All rights reserved. Reproduction of this publication in any form without prior written permission is forbidden. The information contained herein has been obtained from sources believed to be reliable. Gartner disclaims all warranties as to the accuracy, completeness or adequacy of such information. Gartner shall have no liability for errors, omissions or inadequacies in the information contained herein or for interpretations thereof. The reader assumes sole responsibility for the selection of these materials to achieve its intended results. The opinions expressed herein are subject to change without notice