AMORPHOUS oxide semiconductor (AOS) thin-film

Transcription

1 2900 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015 Reliability of Crystalline Indium Gallium Zinc-Oxide Thin-Film Transistors Under Bias Stress With Light Illumination Kyung Park, Hyun-Woo Park, Hyun Soo Shin, Jonguk Bae, Kwon-Shik Park, Inbyeong Kang, Kwun-Bum Chung, and Jang-Yeon Kwon Abstract We investigate the effect of crystalline indium gallium zinc-oxide (c-igzo) thin films on device performance, and evaluate the device reliability of c-igzo under positive/ negative bias stress with/without illumination. The crystal structure of deposited-igzo thin film is controlled by annealing temperatures, and the transition from an amorphous to a crystalline structure is observed at above 800 C. Even though the c-igzo thin-film transistors (TFTs) exhibit lower carrier mobility, compared with amorphous IGZO (a-igzo) TFTs, the remarkable improvement of the device reliability for the c-igzo TFTs is observed especially under the bias stress with illumination. This comes from lower defect density compared with the a-igzo film. Index Terms Crystallization, electronic structure, indium gallium zinc-oxide (IGZO) thin-film transistors (TFTs), oxide semiconductor, reliability. I. INTRODUCTION AMORPHOUS oxide semiconductor (AOS) thin-film transistors (TFTs) have considerably attracted attention for high-end and large area displays, such as active-matrix liquid crystal displays, active-matrix organic light-emitting diodes, and flexible displays, due to their high field-effect mobility, good uniformity, low process temperature, and high transparency to visible light. On the other hand, these displays are not easily realized by the conventional Manuscript received April 9, 2015; revised July 11, 2015; accepted July 15, Date of publication August 5, 2015; date of current version August 19, This work was supported in part by the Ministry of Science, ICT and Future Planning, Korea, through the IT Consilience Creative Program, supervised by the Institute for Information and Communications Technology Promotion, under Grant IITP-2015-R , and in part by Dongguk University through the Dongguk University Research Fund of The review of this paper was arranged by Editor B. Kaczer. K. Park is with the Yonsei Institute of Convergence Technology, Yonsei University, Incheon , Korea ( kyungpark@yonsei.ac.kr). H.-W. Park and K.-B. Chung are with the Division of Physics and Semiconductor Science, Dongguk University, Seoul , Korea ( mnphwcj@dongguk.edu; kbchung@dongguk.edu). H. S. Shin, J. Bae, K.-S. Park, and I. Kang are with the LG Display Research and Development Center, LG Display, Paju , Korea ( mheeshin@lgdisplay.com; jonguk@lgdisplay.com; pius@lgdisplay.com; ibkang@lgdisplay.com). J.-Y. Kwon is with the Yonsei Institute of Convergence Technology, Yonsei University, Incheon , Korea, and also with the School of Integrated Technology, Yonsei University, Incheon , Korea ( jangyeon@yonsei.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED Si-based technology, such as amorphous Si (a-si) and low-temperature poly-si (LTPS), because the a-si exhibited the lack of reliability and the LTPS was also difficult to obtain the large area uniformity, which were required for highperformance display applications [1]. However, despite these advantages of the AOSs, most of the AOSs fundamentally have instability issues, due to electrical stress and environment conditions, such as light, temperature, and humidity during driving devices [2] [4]. It has already been reported that the mentioned instability, the shifts of threshold voltage (V th ), comes from the trapping of charge carrier between oxide semiconductor and gate insulator or semiconductor itself [5] [7]. Electron trapping at the interface between gate dielectric and oxide semiconductor by positive bias stress (PBS) or oxygen absorption to the AOS surface by ambient conditions, which can serve as a suppressor for the carrier concentration, could generate the positive V th shift due to reduction of the carrier concentration. On the other hand, the trapped holes, which were generated by either negative bias stress or light illumination, could cause the negative V th shift. This is one of the key barriers for realizing the high-performance displays, because the driving transistors are operated under electrical bias as well as exposure of visible light. Until now, many studies have been proposed to improve the device instability, such as altering the device structure, gate insulator material, annealing condition, and semiconductor material, as well as using a passivation layer [8] [11]. Most of the proposed techniques were based on an amorphous structure itself. Here, we suggest another approach to overcome the device instability, not on the basis of the amorphous structure. Recently, the c-axis aligned crystal (CAAC)-indium gallium zinc-oxide (IGZO) TFTs were reported as a transistor for display driving [12], [13]. Interestingly, it has been reported that the CAAC-IGZO TFTs exhibited superior reliability against various stress conditions, such as bias stress and/or light illumination. It was caused by the lower defect levels of a CAAC-IGZO film than the conventional amorphous IGZO (a-igzo), which is a widely investigated material [13]. In addition, the authors insisted that only a specific crystal structure with CAAC shows the improved reliability of a device. Even though this is a remarkable enhancement for realizing the high-performance displays, it is not yet clear that this enhancement comes from the IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 PARK et al.: RELIABILITY OF c-igzo TFTs UNDER BIAS STRESS WITH LIGHT ILLUMINATION 2901 specific crystal structure (CAAC) or the conventional phase transformation from amorphous to crystalline. If the conventional crystalline structure also shows the improved reliability like the CAAC structure, it is strongly expected that the possibility of various technologies for crystallization can be opened for a high reliable device. In this paper, we studied the effects of the crystalline IGZO (c-igzo), which was used as a channel material in a TFT structure, on the device performance, specially focused on the device instability. The crystal structure and the microstructure of the IGZO thin films were preferentially investigated before measuring the electrical properties of fabricated-igzo TFTs, in order to confirm the film structure according to the annealing temperature. After that, the electrical properties of the c-igzo TFTs as a function of thermal treatment were measured compared with the conventional a-igzo TFTs, without applying any stress conditions. Finally, the effects of c-igzo on the device reliability were systematically analyzed under both the PBS and the negative bias stress, with/without light illumination with a constant wavelength and intensity. In addition, to understand the performance of an evolution device, depending on the crystallization in IGZO, the band structure and the electronic structure of unoccupied states in the conduction band (CB) and band-edge states of the IGZO thin films were investigated as a function of the annealing temperature. Based on experimental results, we propose that the clear relationship between the device reliability and the c-igzo, as well as the crystal structure itself, plays an important role in the device reliability rather than the specific crystal structure such as a CAAC structure. II. EXPERIMENTAL DETAILS A. Fabrication Procedures of IGZO TFTs A bottom-gated IGZO TFT was fabricated on a highly doped p-type Si wafer with a resistivity of cm, which was used as both substrate and gate electrode. A thermally grown 100-nm-thick SiO 2 was used as a gate insulator. The overall process flow of the fabricated-igzo TFT used in this paper is shown in Fig. 1. Then, a 100-nm-thick IGZO was deposited on SiO 2 /p + Si using a RF sputtering system with an IGZO target having a In 2 O 3 :Ga 2 O 3 :ZnO molar ratio of 1:1:1 and patterned with 1000 μm 500 μm by a liftoff process. The RF power of 100 W and a pressure of 5 mtorr were measured in an Ar and O 2 mixture gas during IGZO deposition. The oxygen partial pressure [P(O 2 ) O 2 /Ar + O 2 ] was maintained at the constant value of 1.6% during the IGZO deposition. To eliminate the interaction between an electrode and a channel by thermal treatment, all samples were annealed before the source/drain (S/D) electrode formation using a tube furnace at temperatures of 300 C, 600 C, 800 C, and 1000 C in air ambient for 1 h, respectively. After that, a 150-nm-thick Mo was deposited using a dc sputtering system and patterned via a liftoff process as the S/D electrode. The channel length and width of the a-igzo TFTs, used in this experiment, were fixed at 50 and 100 μm, respectively. For a detailed material crystallization Fig. 1. Schematic of overall bottom-gated IGZO TFT fabrication. (a) SiO 2 /p + Si substrate. (b) IGZO deposition with a pattern of 1000 μm 500 μm by the RF sputtering system. (c) Postdeposition annealing using tube furnace with various temperatures in air ambient for 1 h. (d) Patterned Mo as a S/D electrode. (e) Plan-view image of the device used in this paper. process of the samples as a function of the annealing temperature, the stacked IGZO/SiO 2 /Si samples were fabricated without patterning process. B. Analysis and Electrical Properties of IGZO Thin Films The crystallization process of the IGZO thin films was confirmed by X-ray diffraction (XRD) and high-resolution transmission electron microscopy (HR-TEM). The chemical composition and film density in IGZO with elevating annealing temperature were investigated by inductively coupled plasma atomic emission spectroscopy (ICP-AES) and Rutherford backscattering (RBS), respectively. Both electrical characteristics and reliability of the fabricated TFT devices were measured using a semiconductor parameter analyzer (Keithley SCS-4200) under dark ambient. In addition, the band alignments, including the bandgap and band offset, were investigated by spectroscopic ellipsometry (SE) and X-ray photoelectron spectroscopy (XPS). The SE spectra were obtained by a rotating analyzer system with an auto retarder, in the range of ev, with incident angles of 65, 70, and 75. The XPS spectra were measured using a monochromatic AlKα X-ray source, with a pass energy of 20 ev. Finally, to examine the electronic structure near the CB, near-edge X-ray absorption spectroscopy experiments were performed using total electron yield mode in BL-10D of Pohang Accelerator Laboratory in Korea. III. RESULTS AND DISCUSSION A. Properties of IGZO Thin Films Depending on Temperatures Fig. 2(a) shows the XRD spectra obtained from annealed IGZO films at 300 C, 600 C, 800 C, and 1000 C. It is hard to find the diffraction peaks of crystalline phase for the IGZO films annealed at 300 C and 600 C. It indicates that the IGZO thin film could maintain an amorphous phase of up to 600 C. However, when annealed at 800 C, a spectrum with the hexagonal In 2 Ga 2 ZnO 7 (102) and (105) peaks has

3 2902 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015 Fig. 2. (a) XRD spectrum obtained from the samples annealed at different temperatures. (b) Chemical composition of deposited-igzo thin film by analyzing the ICP-AES. Fig. 4. Representative transfer curves of the a-igzo TFT as a function of the annealing temperatures at 300 C, 600 C, 800 C, and 1000 C. In addition, to analyze in detail the crystalline structure, selected area electron diffraction (SAED) was analyzed, as shown in Fig. 3(a) (d). As a result, there were clear crystalline spots with various directions in the pattern of annealing at 800 C and 1000 C, suggesting that the IGZO thin films had a polycrystalline structure. The halo pattern was observed in the pattern of annealing at 300 C and 600 C, which indicates an amorphous structure. Another interesting result is that the crystallinity of IGZO annealed with 1000 C was slightly increased in Fig. 3(d), although there was no observation in the change of the crystallinity on the IGZO films by the XRD spectrum. Fig. 3. Cross-sectional bright field HR-TEM image showing the crystallinity of IGZO annealed at (a) 300 C, (b) 600 C, (c) 800 C, and (d) 1000 C. Insets of (a) (d): SAED patterns with various annealing temperatures. been produced. These spectrums provide a critical clue to understand the crystallization of the IGZO thin films, indicating that the crystallization of the IGZO thin film probably started in local areas at the temperature between 600 C and 800 C. There was no significant variation of peak intensity between 800 C and 1000 C, which means that the change of crystallinity in the entire films was not observed with increasing temperature. Interestingly, the chemical composition in the IGZO thin films, obtained from the ICP-AES, as shown in Fig. 2(b), showed a little change by the annealing temperatures. It is noted that the IGZO thin films, which were annealed at above 800 C, obviously had a crystalline structure with a small change of chemical composition in the IGZO films, through the XRD and ICP-AES analysis. For the detailed microstructural study of the IGZO thin films, as a function of the annealing temperature, the HR-TEM technique was performed. Fig. 3(a) (d) shows the HR-TEM images, which are consistent with the XRD results. Both the devices annealed at 800 C and 1000 C exhibited the localized crystallization of the IGZO thin films. B. Electrical Characteristics of IGZO TFTs Depending on Temperatures To study the effects of the crystallinity of the deposited-igzo thin films on the device performance, the electrical properties of the IGZO TFTs were measured using probe-station under dark ambient. Fig. 4 shows the representative transfer characteristics of the IGZO TFTs as a function of the annealing temperature; a measurement of the source-to-drain current (I DS ) with the gate voltage (V G ) varying from 40 to 40 V at a fixed drain voltage (V D ) of 10 V and the electrical properties of all devices are summarized in Table I. As shown in Fig. 4, a transfer curve of the IGZO TFT as a function of the annealing temperature can be divided by two groups on the basis of V th characteristic as follows: regions 1 (300 C and 600 C: a-igzo) and regions 2 (800 C and 1000 C: c-igzo). The TFT devices having an amorphous structure, which were annealed at 300 C and 600 C, exhibited relatively higher mobility and lower swing than those with a polycrystalline structure annealed at 800 C and 1000 C. When the c-igzo was used as a channel layer replacing the conventional a-igzo, the V th tended to negatively shift, and the device performance was slightly deteriorated. In the case of mobility, as the annealing temperature was increased, the mobility gradually decreased from 10 to 2 cm 2 /V s. The grain boundaries generated from the crystallization can disturb the carrier transportation in the IGZO channel. Here, it is notable that the c-igzo TFTs have a negative V th compared with the a-igzo TFTs,

4 PARK et al.: RELIABILITY OF c-igzo TFTs UNDER BIAS STRESS WITH LIGHT ILLUMINATION 2903 TABLE I ELECTRICAL PROPERTIES OF IGZO TFTs AS A FUNCTION OF ANNEALING TEMPERATURE,SUCH AS MOBILITY, SUBTHRESHOLD SWING, AND V th Fig. 6. Change of V 1nA versus stress time and various stress conditions. (a) and (b) PBS (V G = 40 V). (c) and (d) Negative bias (V G = 40 V) stress. (b) and (d) Device was exposed with a constant light illumination. (a) and (c) Device was exposed without a constant light illumination. Fig. 5. (a) Extinction coefficient measured by SE. (b) XPS spectra near valence band. (c) Schematic energy level diagram including the relative energy position of the Fermi level (EF) with respect to the conduction band minimum and valence band maximum. despite of slight performance deterioration. This V th difference was probably caused by defect levels, which are mainly located near valence band (VB) and caused by oxygen vacancy. In addition, to explain the evolution of device performance behavior, depending on an annealing temperature, more in-depth studies were systematically investigated by analyzing the band structure of IGZO with respect to the annealing temperature and the results are described in detail. C. Band Structure of IGZO Thin Films Depending on Temperatures Fig. 5(a) (c) shows the bandgap (E g ) and the VB spectra measured by the SE and XPS, and the schematic energy level diagram of InGaZnO as a function of the annealing temperature, respectively. As the annealing temperature is increased, the bandgap is increased from 3.41 ev for 600 C to 3.61 ev for 1000 C. The VB offset ( E VB ) between the Fermi level and the VB maximum is slightly increased as well. As a result, the CB offset ( E CB = E g E VB ) is changed from 0.26 to 0.41 ev depending on the annealing temperature, which represents the smaller value in the IGZO film annealed at 300 C and 600 C. The CB offset is strongly related to the carrier concentration, and the smaller CB offset for the a-igzo film indicates the higher carrier concentration [14]. These results were well consistent with our result of the carrier concentration, measured by hall measurement, and thus the higher electron mobility and performance in the a-igzo TFT could be explained compared with the c-igzo TFT. In summary, the large CB offset, which was caused by high-annealing temperature, acts as a barrier to the carrier generation, resulting in low mobility. However, such low mobility can be enough improved by using the conventional techniques, such as altering the cation composition and designing the pixel/module. D. Device Reliability: a-igzo Versus c-igzo After measuring the initial electrical properties of the IGZO TFTs, we evaluated the device reliability under bias and light illumination stress as a function of the stress time. The change in V 1nA is shown in Fig. 6(a) (d). Here, V 1nA denotes the gate voltage at the I DS of 1 na. During the PBS, it has already been known that V 1nA is positively shifted due to electron trapping at the interface between the gate insulator and the channel layer or channel itself. In addition, the light illumination can generate the photoinduced holes, which contribute to charge trapping and the negative shift of V 1nA [15]. As shown in Fig. 6(a), after the PBS under the positive bias of 20 V for 120 min, a large V 1nA of a device with a-igzo was positively shifted due to much electron traps. However, there was a small V 1nA shift under positive bias illumination stress (PBIS), because the holes caused by light

5 2904 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 9, SEPTEMBER 2015 illumination hindered the positive shift of V 1nA,asshown in Fig. 6(b). On the contrary, in the case of c-igzo, the shift of V 1nA could not be nearly found under both the PBS and the PBIS, indicating that c-igzo has less electron traps density than a-igzo. In other words, the high crystallinity of IGZO can cause a decrease in the electron trap density, resulting in improvement of the device stability. The results under negative bias stress, as shown in Fig. 6(c) and (d), were similar to the former PBS and PBIS. In addition, in the case of negative bias illumination stress (NBIS), the light illumination accelerates the negative V 1nA shift, due to the synergy effect between the induced holes generated by the light illumination and negative bias. In particular, after the NBIS for 120 min, V 1nA of the IGZO TFT with a crystal structure shows a little change, whereas that with an amorphous structure exhibited an abundantly negative shift. This difference in V 1nA can be explained by the deeply occupied subgap states near the VB maximum due to oxygen vacancies, as mentioned above. This suggests that the amorphous structure contains more sites for the charge trapping than the crystal structure. According to the reported literatures, the defect levels in the bandgap of the IGZO as a function of the crystal structure were measured using the constant photocurrent method [16] [18], which can analyze the light absorption coefficient caused by defect levels in the IGZO thin films [12], [19]. It was reported that the CAAC-IGZO had less defect levels than the conventional IGZO, which leads to a better device reliability. In addition, c-igzo has a larger cohesive energy than a-igzo, because a more stable structure has a larger cohesive energy, resulting in a high film density, which is in relation with the defect levels [19]. On the basis of these results, the density of the IGZO films used in this paper was analyzed according to the annealing temperatures using the RBS. As a result, it was found that the film density of the IGZO thin film was slightly increased from to atoms/cm 2 with the increasing annealing temperature from 300 C to 1000 C. It means that the c-igzo thin films have a film density of 1%, which is higher than the conventional a-igzo thin films, probably caused by low defect levels. Although the increase in the film density by thermal treatment was smaller than expected, it may be an important clue enough to evaluate the change of film characteristics. Despite this small change in the film density, the crystallization of the IGZO thin films can obviously affect the device reliability regardless of the crystallinity and a specific crystal structure, such as a CAAC structure. Consequently, it can be supposed that the reliability of the IGZO TFT, under various stress parameters, is clearly sensitive to the crystallinity of IGZO. Although a high-annealing temperature is needed for the IGZO crystallization, such high-annealing temperature can be easily reduced using the conventional crystallization process developed for Si material. E. Near-Edge X-Ray Absorption Spectroscopy To figure out the electronic structure of the unoccupied states in the CB and band-edge states of the IGZO films, the analysis was done by X-ray absorption spectroscopy (XAS) measurements as a function of the annealing temperature, Fig. 7. (a) Normalized XAS O K1 edge spectra (top) and second-derivative O K1 edge spectra (bottom) as a function of annealing temperature, respectively. The Gaussian fits, from which the energy positions were determined by the minimum of second derivative, represent the crystal-field splittings of sp orbitals. (b) Band-edge states below the CB at 530 ev were shown as a function of annealing temperature. as shown in Fig. 7. Renormalizations of the XAS spectra were carefully performed by subtracting the X-ray beam background and scaling of edge level from the raw data. The qualitative changes and the comparison of the CB features, such as the number and distribution of the unoccupied states, could be analyzed by the renormalizations of XAS spectra [20]. The normalized oxygen K1 edge spectra of the IGZO films are directly related to the oxygen p-projected states of the CB, which consists of unoccupied hybridization orbitals for In 5sp + O 2p, Ga 4sp + O2p,andZn4sp+ O 2p [21], [22]. Fig. 7 also includes the second-derivative analysis of the O K1 edge spectra. This analysis is sensitive to minute changes in the XAS spectral feature, which is very useful in interpreting the crystal field splitting of representative orbital states. Based on the second-derivative spectrum analysis, the Gaussian fits of hybridized orbital states were carefully performed, including the band-edge states below the CB. Two distinct XAS peaks composed of four Gaussian fits imply the hybridization of In 5s, Ga 4s, Zn 4s + O 2p and In 5p, Ga 4p, Zn 4p + O 2p from the low photon energy [21]. The interesting finding is the sharpening of two peaks with the increase of

6 PARK et al.: RELIABILITY OF c-igzo TFTs UNDER BIAS STRESS WITH LIGHT ILLUMINATION 2905 the annealing temperature, which indicates the crystal-field splitting due to the changes of a physical structure under highannealing temperature, resulting in improvement of the device reliability. In addition, when the changes of the third and fourth Gaussian fits considered, the relative ratio of p orbital hybridization with the directionality compared with s orbital with spherical symmetry is enhanced by the high annealing temperature. This modification of the orbital hybridization could induce the degradation of device performance, because of the splitting of the unoccupied states and the mixture of directional p orbitals. This can increase the device stability under various stress conditions, despite of the difficulty of charge transport in the CB. Another meaningful finding is the analysis of the band-edge state below the CB, as shown in Fig. 7(b). The band-edge states after high-annealing temperature at 1000 C are dramatically reduced compared with the other annealing temperature. This change could be related to the relative decrease of an orbital boundary by the uniform composition of the orbital hybridization, as compared with the IGZO film annealed at the low temperature. As a result, the reduction of the band-edge states within the bandgap is correlated to the improvement of reliability due to the decrease of the charge trapping and scattering. IV. CONCLUSION In summary, we investigated the reliability of the c-igzo TFTs under the PBS/negative bias stress with light illumination, compared with the conventional a-igzo TFTs. The IGZO structure could affect the device performance, especially the V th characteristic, according to the amorphous and crystalline structures. Furthermore, by increasing the crystallinity, the device stability was significantly improved; this is probably due to the decrease of trap density between the gate insulator and the channel layer or the channel itself. Thus, it is clear that the device reliability, which was induced by various stress conditions, can be improved through the crystallization of the IGZO film. In particular, this improvement is caused by the crystallization itself, and not the specified crystal structure, such as the CAAC structure. Even though many reports have been focused on the AOS film for the last ten years, the crystalline oxide semiconductor could be one of the key solutions for the next-generation active matrix displays and electronics because of their superior stability. REFERENCES [1] J. S. Park, W.-J. Maeng, H.-S. Kim, and J.-S. Park, Review of recent developments in amorphous oxide semiconductor thin-film transistor devices, Thin Solid Films, vol. 520, no. 6, pp , Jan [2] K.-H. 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