Design and Analysis of Wafer-Level CSP With a Double-Pad Structure. Ji-Cheng Lin, Hsien-Chie Cheng, Member, IEEE, and Kuo-Ning Chiang

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1 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 1, MARCH Design and Analysis of Wafer-Level CSP With a Double-Pad Structure Ji-Cheng Lin, Hsien-Chie Cheng, Member, IEEE, and Kuo-Ning Chiang Abstract Wafer level chip scale packaging (WLCSP) is very promising for the miniature of packaging size, the reduction of manufacturing cost, and the enhancement of the package s performance. However, the long-term board level reliability of integrated circuit (IC) devices using wafer level packaging with large distances from neutral point (DNP) is still not fully solved. This research proposes a novel, alternative WLCSP design for facilitating higher board level reliability. The main feature of the novel WLCSP is basically in its double-pad structure (DPS) design in the interface between solder joints and silicon chip. To characterize the solder joint reliability of the DPS-WLCSP, a three-dimensional (3-D) nonlinear finite element (FE) modeling technique is employed. Based on the FE modeling, the numerical accelerated thermal cycling (ATC) test is performed under the JEDEC temperature cycling specification. The validity of the proposed FE modeling is verified by using an optical measurement method Twyman Green interferometer. By the derived incremental equivalent plastic strain, the cumulative cycles to failure in solder joints associated with these four WLCSP are assessed based on a modified Coffin Manson relationship. The modeled fatigue life is compared against the experimental results that adopt a two-parameter Weibull distribution to characterize cycles-to-failure distribution. For comparison, the investigation also involves several existing types of WLCSP, including the conventional (C-WLCSP), the copper post (CP-WLCSP), and the polymer post (PP-WLCSP), and solder joint reliability performance among these WLCSP packages is extensively compared. The results demonstrate that the DPS-WLCSP design not only has potential for enhancing the corresponding solder joint reliability but is also particularly effective in manufacturing process and cost. And finally, some reliability-enhanced design guidelines are provided through parametric design of the DPS. Index Terms Accelerated thermal cycling test, finite element (FE) modeling, solder joint reliability, Twyman Green interferometer, wafer level packaging. I. INTRODUCTION THE current trend of electronic devices is toward more integral functionality, higher speed, and better electrical performance; thus, an electronic package that has lower signal degradation, higher reliability and lower cost is of great Manuscript received July 1, 2004; revised December 1, This work was supported in part by the National Science Council of Taiwan, R.O.C., under Project NSC E , and in part by ACE Technology Company, Inc., Hsinchu, Taiwan. This work was recommended for publication by Associate Editor R. S.-W. Lee upon evaluation of the reviewers comments. J.-C. Lin is with the Delta Electronics, Taipei 114, Taiwan, R.O.C. H.-C. Cheng is with the Department of Aerospace and System Engineering, Feng Chia University, Taichung 407, Taiwan, R.O.C. K.-N. Chiang Advanced Microsystem Packaging and Nano-Mechanics Research Laboratory, Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu 300, Taiwan, R.O.C. ( knchiang@pme.nthu.edu.tw). Digital Object Identifier /TCAPT Fig. 1. WLCSP for 128M SDRAM. demand. Wafer level chip scale packaging (WLCSP) technologies provide a very promising alternative in fitting the high performance requirements for today s electronic packaging applications. As compared to the flip chip (FC) packaging, almost all of the package process is conducted at the wafer level, and it does not need an underfill material to protect solder joints from thermal deformation that is generally induced from the coefficient of thermal expansion (CTE) mismatch between silicon chip and printed circuit board (PCB). As a result, the existing difficulties occurred in the FC packaging, such as reworkability and known good die (KGD), could be relieved. The main feature of the packaging approaches is its space efficiency and the potential for package cost reduction due to that a great number of dice are processed in parallel rather than serial as the FC technology. Recently, as a substitute of thin small outline packages (TSOP), the packaging technologies are employed in memory applications such as flash and dynamic random access memory (DRAM) modules (Fig. 1) etc. It has been acknowledged that solder joint reliability is still the most critical and challenging issue in the development and extensive use of the WLCSP technology for practical applications. Notice that the industry prospects of board level reliability for wafer level packages are based on current standards for plastic packages. In general, board level reliability expectations are determined by the associated operating environment and intended applications. For examples, based on Amkor Technology, Inc., board level reliability requirement for consumer applications is 300 cycles, for portables and telecom indoors is 600 cycles, for computer applications, such as desktops, laptops and workstations, is 900 cycles, for auto under the good and commercial avionics is 1500 cycles, and for military and auto on engine is 2400 cycles, when subjected to a C 125 CATC test with 20 min ramp and 10 min dwell at both the high and low temperature zones and the duration of 60 min per cycle. Thus, for memory applications, 1000 thermal cycles are considered as /$ IEEE

2 118 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 1, MARCH 2005 Fig. 2. Cross section of a variety of WLCSP. (a) C-WLCSP. (b) CP-WLCSP. (c) PP-WLCSP. (d) DPS-WLCSP. Fig. 4. crack. Redistribution trace with a deep trench, steep shape angle, and possible Fig. 5. Optical micrographs of the cross section of a PP-WLCSP. Fig. 3. Optical micrographs of the cross section of a typical, conventional WLCSP. a typical standard. The factors influencing WLCSP solder joint reliability and failure mechanisms include the configuration of packages and the geometry and materials of components, etc. The most common and effective approach for WLCSP to enhance its solder joint reliability is through the application of stress buffer layer [1] [3]. Note that the standard WLCSP associated with a single stress buffer layer, as shown in Figs. 2(a) and 3, is simply termed as the conventional WLCSP (C-WLCSP). Basically, it holds a simple configuration and low cost, and more importantly, can provide considerable solder joint reliability as the stress buffer layer height is sufficiently large. The stress buffer layer, which is typically made of a polymer material, is deposited on the silicon wafer. It serves as not only a dielectric layer but also a compliant interposer between silicon chip and solder bump, which makes the packaging structure become more compliant, and accordingly, reduces thermal stresses. A thick buffer layer can be processed in a number of ways, such as multiple spinning etc. Under the current manufacturing and photolithography process capability, to establish a thick stress buffer layer using multiple spinning is possible but challenging and expansive. For examples, it would not be easy to construct reliable bonding between two adjacent stress buffer layers. On the other hand, if instead using the standard spinning coating technique, the spinning speed should be sufficiently low and the viscosity of the polyimide should be considerably high for spinning a thick stress buffer layer. Unfortunately, these would make the manufacturing process ineffective, produce a nonuniform stress buffer layer, and perhaps, damage the electrical circuits on wafer because of the application of a viscous substance for spinning coating. Besides, it would be very difficult to perform light exposure in the bottom side of the thick stress buffer layer. Even if the fabrication process for thick stress buffer layer were achievable, e.g., by way of multiple spinning, the increase of the stress buffer layer height would accordingly create a deep trench of vias. A deep trench would make difficult the construction of the vias using electroplating process, and lead to a poor redistribution trace with a steep shape angle if the diameter of vias remains unchanged. Most importantly, a very steep angle would result in some stress concentration areas on top and bottom of the redistribution traces, and eventually, might turn into copper trace cracking, as shown in Fig. 4. Generally, under the same die size and test condition, the more the number of solder joints and/or the bigger the bump size [4], the better the solder joint reliability. In addition, the thicker the stress buffer layer, the better the solder joint reliability if failure mechanism remains unchanged. In literature, many advanced WLCSP designs (see, e.g., [1] [11]) are being developed in order to resolve the above issues. For examples, Fujitsu Inc. developed the so-called SuperCSP [3] for enhancing the corresponding solder joint reliability by means of a copper post design underneath these bumps, as shown in Fig. 2(b); Tessera proposed the so-called WAVE [5], which uses a thick stress decoupler layer to reduce solder joint stress and applies bond ribbons (or flexible link) on the underside of the film to join the bond pads on wafer; Bakir et al. introduced a WLCSP with embedded air-gap [6], which could basically provide a compliant structure and higher electrical performance; Fraunhofer IZM/TU-Berlin proposed a double-solder-bump WLCSP design [8] to increase structure compliance; Flip Chip Technologies introduced the so-called Ultra CSP [9] based on simple bump on nitride redistribution technology with BCB as the interlayer dielectric; ACE Technology Inc. presented a more compliant WLCSP design by way of the use of polymer post [10] (see Figs. 2(c) and 5); and Dow Corning recently released a lowmodulus, stencil-printable silicone and a low-stress photo-patternable silicone materials [11] for such as stress-buffer layer applications. It has been extensively reported that these WLCSP designs could enhance the corresponding solder joint reliability,

3 LIN et al.: DESIGN AND ANALYSIS OF WAFER-LEVEL CSP WITH A DOUBLE-PAD STRUCTURE 119 as compared to the conventional WLCSP. For instances, Fujitsu and IZM/TU-Berlin have reported that their packages, SuperCSP and double-solder-bump WLCSP design, respectively, could meet 1000 thermal cycle spec. To continuously seek a more advanced, reliable and cost-effective WLCSP design would be the primary goal of design engineers and researchers. In this study, a novel WLCSP design with a double-pad structure (DPS-WLCSP) is introduced as an alternative and potential solution to the above issues. The electro-mechanical interconnects between these two pads are provided by a number of conductive copper columns, as shown in Figs. 2(d) and 7(b). They not only could provide a good compliance to solder joints but also hold a thicker stress buffer layer. Apparently, the DPS-WLCSP can possibly facilitate higher solder joint reliability. For readily characterizing the solder joint reliability of the DPS-WLCSP, a three-dimensional (3-D) nonlinear FE modeling technique is applied to simulate ATC testing. Modeling details and assumptions made in the simulations are described. It is important to note that the estimation of solder joint reliability requires precise strain information. However, in a nonlinear FE analysis, a highly mesh-sensitive, strain field, which is generally the maximum one, would be induced at the corners of solder joints due to a significant geometry/material change. To characterize the concentration strain, the finite-volume-weighted averaging technique proposed in [12] is employed. With the averaged strain, the corresponding cumulative cycles to failure are then estimated based on the modified Coffin Manson relationship [13] [16]. The validity of the proposed FE modeling is confirmed by way of Twyman Green interferometry measurement. Besides, to substantiate the feasibility of the proposed DPS-WLCSP design, results from other types of WLCSP involving the C-WLCSP, the CP-WLCSP, and the PP-WLCSP, are also provided in this investigation. Furthermore, for further validation of the proposed FE modeling, two experimental ATC tests are performed, associated with PP-WLCSP and C-WLCSP packages, respectively. The testing results are presented in a two-parameter Weibull distribution to characterize failure distribution. The fatigue life predicted by FE simulations is extensively compared against the experimental. In addition, the solder joint reliability performance of these WLCSP designs is also compared. At last, through parametric design of the double-pad structure, some reliability-enhanced design guidelines are provided. The associated design parameters comprise the number, height, diameter and distributing layout of copper columns in the double-pad structure. II. FABRICATION OF THE DPS-WLCSP The manufacturing process of the DPS-WLCSP is considerably simple and compatible to the standard WL packaging process; hence, the manufacturing cost of the DPS-WLCSP can be effective. The fabrication process, shown in Fig. 6, can be briefly categorized into seven manufacturing steps and these steps are associated with at most four mask processes. First of all, by way of the spin coating technique, a stress buffer layer is coated onto a silicon substrate, on which both electrode pads and passivation layer are defined. By a mask process, the first stress buffer layer is patterned to uncover these electrode pads, Fig. 6. Fabrication process of the DPS-WLCSP. Fig. 7. Fabrication of a 48-I/O DPS-WLCSP for a SDRAM application. (a) SDRAM. (b) Cross section of the bump and DPS with only one copper column (diameter: 60 m). as shown in Fig. 6(b). In general, the above processes are completed in a dedicated IC foundry. The wafer is then delivered to the packaging house for subsequent processes. In this aspect, the aforementioned mask process is neglected from the count of mask processes needed in the fabrication of the DPS-WLCSP. The wafer is further processed to create under-bump-metallurgy (UBM) layers on the stress buffer layer through sputtering, as shown in Fig. 6(c). By using the first mask process to define the redistribution layer trace layout, the trace can then be made through a standard electroplating process. It can be easily observed that for the intact of these redistribution traces, the deposited thickness of the first stress buffer layer should be restricted. Generally, 5 20 m is commonly used. Fig. 6(c) shows a silicon substrate with metal pads, a stress buffer layer and the redistribution trace after removal of the photoresist. Next, the second stress buffer layer is coated onto the substrate surface. The buffer layer is further patterned by the second mask process in order to create the channel of copper columns [see Fig. 6(d)]. The copper columns are then constructed by way of electroplating process. When copper spills out of these channels, copper pads can be formed, as shown in Fig. 6(e). Unlike the conventional redistribution process, this double-pad structure will be unlikely to cause the failure of the redistribution trace as applied to a thick stress buffer layer. Furthermore, a layer of solder mask is coated on the second stress buffer layer, and the corresponding location of the copper pads is patterned through the third mask process, as shown in Fig. 6(f). At last,

4 120 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 1, MARCH 2005 by using standard bumping process, these solder bumps are created, as shown in Fig. 6(g). For better shape and formation of the second copper pad, an additional mask process is suggested in order for the deposition of the copper pad through both sputtering and electroplating processes. The major advantageous features in the novel DPS-WLCSP design is in its flexibility in adjusting the thickness of the second stress buffer layer for enhancing the corresponding solder joint reliability without concern of possible damage in the deposited redistribution layer trace. Based on the aforementioned process, the DPS-WLCSP prototypes are designed and fabricated, particularly for a 128M SDRAM application. The 8-in wafer, shown in Fig. 1, is applied for the fabrication, and a sample of the fabricated, 46 I/O DPS- WLCSP is presented in Fig. 7(a). The DPS contains five copper columns with a diameter 30 m. Fig. 7(b) shows an example of the cross section of the bump attached to a double-pad structure with one copper column. For comparison, the C-WLCSP, PP-WLCSP, and CP-WLCSP are also fabricated. The size of the chip is mm, the ball pitch is 0.75 mm and the number of solder balls is 46. It should be noted that the compliance of the DPS is dependent of the number of copper columns. Those bumps at the corners of the chip are dummy in terms of electrical conduction and signal pass, and are designed specially for solder joint reliability enhancement; as a result, there are only 42 functional I/Os in the design. III. THERMAL FATIGUE LIFE PREDICTION In general, thermal loading is the main cause of the failures of electronic devices [2], [7]. When an electronic package is subjected to temperature cycling loading, solder bumps would experience cyclic, thermo-mechanical deformations, resulting in the fatigue failure of solder joints. In order to predict the fatigue life of the solder bumps, a modified Coffin Manson relationship [13] [16] is applied where is the mean cycles to failure, denotes the plastic shear strain range, and are a constant, respectively. For eutectic solder, the average value of and at C, 35 C, and 125 C determined by Solomon [15] is 1.96 and , respectively. For a thermal-mechanical problem, the resulted total strains/stresses are generally multi-axial, and thus, the equivalent plastic strain range is applied in this study, defined as (2) shown at the bottom of the page, where, and, and are the incremental plastic strain range components at the most critical solder bump. Accordingly, (1) can be then modified as and and become 1.96 and , respectively [16]. (1) (3) Fig. 8. Three-dimensional FE models associated with these four types of WLCSP. (a) One quarter of WLCSP. (b) C-WLCSP. (c) CP-WLCSP. (d) PP-WLCSP. (e) DPS-WLCSP. IV. FE MODELS The investigation involves four different types of WLCSP, including the C-WLCSP, the PP-WLCSP, the CP-WLCSP, and the DPS-WLCSP. In addition, in the double-pad structure in the DPS-WLCSP, five copper columns are included, and the corresponding distributing layout is shown in Fig. 17(a). The diameter of these copper columns is 30 m. Numerical modeling of these test assemblies is performed in 3-D solid modeling using FE analysis, and the commercial software ANSYS is responsible for modeling and simulating the stress/strain behaviors of these packages under thermal cycling loading. Fig. 8(a) shows an example of mesh for the 3-D model associated with the DPS-WLCSP, and Fig. 8(b) (e) present a local view of the FE mesh at one of the solder joints in the C-WLCSP, PP-WLCSP, CP-WLCSP, and DPS-WLCSP, respectively. The geometry of the models is detailed enough to specify all the components, including such as a silicon chip, a stress buffer layer, copper pads, solder joints, a solder mask, and a PCB, in addition to the polymer posts, the copper posts, the second stress buffer layer, the copper columns with double pads, etc. It is noted that the geometry profile of the solder joint is determined by using the (2)

5 LIN et al.: DESIGN AND ANALYSIS OF WAFER-LEVEL CSP WITH A DOUBLE-PAD STRUCTURE 121 TABLE I MATERIAL PROPERTIES OF THE FEM MODELS TABLE II PACKAGING DIMENSIONS OF WLCSP surface evolver (see, e.g., [17]). Due to the geometric symmetry, only one quarter of these WLCSP is modeled in the FE analysis. A symmetry boundary condition is imposed on the symmetry plane of the package, and the -dir displacement in the bottom of the interaction of the symmetry planes is constrained to prevent it from rigid body motion during FE analysis. In summary, the FE model size associated with these WLCSP is about elements, and brick elements are, generally, used throughout the entire domain. The material properties of these components are listed in Table I, based on [18]. The geometry dimension of these WLCSP as well as the printed circuit board (PCB) is shown in Table II. In the FE modeling, the solder bump and stress buffer layer are considered nonlinear and temperature-dependent. The temperature-dependent stress/strain relationship of the eutectic solder joints and the stress buffer layer [19], [20] is depicted in Fig. 9(a) and (b), respectively. For charactering the contribution of irreversible plastic deformation to the strain, the rate-independent plastic deformation is modeled by Prandtl Reuss equation and also the kinematic hardening rule. To ensure convergence of the iterations, the full Newton Raphson method is used in the analysis. The stress free temperature is assumed to be room temperature (i.e., 25 C). The thermal cycle profile for the testing is 55 C 125 C with 15-min ramp and dwell times. The duration of each cycle is 60 min. V. VALIDATION OF THE FE MODELING A. Twyman Green Interferometery Measurement To validate the proposed FE modeling, a Twyman Green interferometer system is set up. The Twyman Green interferometer system could measure the real-time, whole-field, out-ofplane displacement of silicon chips subjected to temperature Fig. 9. Temperature-dependent stress/strain curves. (a) Eutectic solder. (b) Polyimide. Fig. 10. Twyman Green interferometry system. loading. The Twyman Green interferometer is shown in Fig. 10, in which a He Ne laser beam with m wavelength is applied. The beam splitter is employed to divide the laser beam into two orthogonal beams. After reflecting from the specimen and the mirror, the interference fringes are captured by a digital camera and a computer system. The out-of-plane displacement

6 122 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 1, MARCH 2005 B. ATC Test Among those major environmental accelerated testing methodologies, ATC testing is generally applied for characterizing solder joint reliability of electronic devices. The testing is conducted based on JEDEC specification [22]. The test vehicles in this investigation include both C-WLCSP and PP-WLCSP packages on a printed circuit test board with a single layer, 1 mm thick. Both them have internal daisy chain that forms a closed loop with daisy chain on the test board. The daisy chain can facilitate the inspection of solder joint failure by means of continuous electrical monitoring. The criterion for an open solder joint is based on the associated cycle life in the first peak (at least 30% increase) of the measured electrical resistance. Generally, as soon as the first peak of the electrical resistance is observed, there are many additional peaks within about 10% of the cycle life. In order to identify the failure site with increased thermal cycles, except the aforementioned daisy chain, an additional electrical copper trace is fabricated in the ATC test board, shown in Fig. 11, for each peripheral solder joint in the package such that the corresponding signal can be independently measured. The thermal cycle profile for the testing is 40 C 125 C with 15-min ramp and dwell times. The duration of each cycle is one hour. There are eight test samples in the testing of the PP-WLCSP and 14 samples for the C-WLCSP. The Weibull distribution is one of the most widely-used lifetime distributions in reliability engineering. It is a versatile distribution that can take on the characteristics of other types of distributions, based on the value of the shape parameter. The estimates of the parameters of the Weibull distribution can be found by way of probability plotting, or analytically, either using the least square or maximum likelihood methods. The method of probability plotting is the least mathematically intensive method for parameter estimation, and is easily implemented by hand. Basically, as the term implies, it involves a physical plot of the data on specially constructed probability plotting paper. To generate the plot, first rank the cycles-to-failure of these test samples in ascending order. Second, obtain their median rank (MR) plotting positions. Basically, median rank is used to obtain an estimate of the unreliability for each failure. It is the value that the true probability of failure,, should have at the -th failure out of a sample of units, at a 50% confidence level. A quick and less accurate approximation of the median rank [23] is given by Fig. 11. ATC test board. (5), which basically depends on the wavelength, can be expressed as [21] where is the interference fringe number. It should be noted that in the application of the Twyman Green interferometer technique, the backside of wafer should be polished or shining for fulfilling measurement. Based on the equation, the resolution of the Twyman Green interferometer is found to be 0.32 m. (4) Then, the probability of reliability or survival,, can be expresses as, where (, and ) is the fatigue life of the th test sample. Then, a two-parameter Weibull distribution is used to characterize failure distribution, in which the Weibull cumulative failure distribution is correlated to the data of cycles to failure. The equation is shown in the following: where is the cumulative failure distribution function after thermal cycling loading, is the number of thermal cycles, is a scale parameter that is the number of thermal cycles with 63.2% failure occurrence, is the shape parameter. Note, that a large is roughly and inversely proportional to the coefficient of variation, and is commonly referred to as characteristic life. The equation results in a straight line if it is rewritten in double logarithm format. Third, on a Weibull probability paper, plot the cycles-to-failure and their corresponding ranks. Fourth, draw the best possible straight line through these points. The slope of the line is the estimate of the shape parameter. Last, the estimate of the scale factor can be easily obtained by finding the cycles-to-failure corresponding to the characteristic life. VI. RESULTS AND DISCUSSION A. Validation by the Twyman Green Interferometry Measuement The FE modeling is first validated through the Twyman- Green interfermetry measurement. Since the backside of the 8-in wafer that is applied for fabrication of the C-WLCSP, as shown in Fig. 3, is polished a priori, it is considered as test vehicle in the measurement. The temperature range in the environmental chamber varies from 25 Cto75 C. The FE model associated with the test vehicle is constructed, and the derived out-of-plane displacement of the silicon chip is shown in Fig. 12(a). On the other hand, the interference fringe pattern of the silicon chip taken from using the Twyman Green interferometer system is presented in Fig. 12(b), which represents the deflection of the assembly around the region where the chip is situated. Evidently, the result trend is consistent between these two approaches. In addition, both these two figures demonstrate that the maximum deformation occurs at the diagonal corner of the chip. Based on (4), the net out-of-plane displacement from the chip center to the corner is 1.27 m. In contrast to the modeled result, which is 1.36 m, the difference is only about 9.0%. B. Validation by the ATC Testing In the PP-WLCSP test vehicle, the corresponding polymer post is 35- m high, the first stress buffer layer 5- m thick and (6)

7 LIN et al.: DESIGN AND ANALYSIS OF WAFER-LEVEL CSP WITH A DOUBLE-PAD STRUCTURE 123 Fig. 12. Out-of-plane deformations obtained from both the FE simulation and Twyman Green interferometry system. (a) FE result. (b) Measurement data. Fig. 14. Cross section of the failure site in the PP-WLCSP. TABLE III MODELED AND EXPERIMENTAL SOLDER JOINT FATIGUE LIFE Fig. 13. Cycles to failure data for solder joints in the PP-WLCSP. the second stress buffer layer 35- m thick. On the other hand, the buffer layer height in the C-WLCSP test vehicle is also 5 m. Other dimension can be found in Table II. Fig. 13 shows an example of a Weibull plot of cycles to first failure for a set of PP-WLCSP test samples. A typical failure mechanism for the PP-WLCSP is shown in Fig. 14. Regardless of the test vehicles, the first failure is detected to occur from the peripheral ring in the corner solder joints with the maximum distance to neutral point. The solder joint cracking is observed at the interface between the solder joint and the polymer post, and the solder joint that is fatigued is located at the site with the maximum distance to neutral point. Based on the experimental data, the estimate of the scale and shape parameters is 392 cycles and 3.42, respectively. Thus, the corresponding characteristic life of the solder joint is 392 cycles. It turns out that the fitting curve-the Weibull distribution correlates pretty much well with the experimental data. Likewise, the characterized solder joint characteristic life associated with the C-WLCSP is 200 cycles, as shown in Table III. The corresponding fatigue life associated with 50% Weibull cumulative failure occurrence based on the obtained cumulative failure distribution function in (6) is 352 cycles and 179 cycles, associated with the polymer-post WLCSP and conventional WLCSP. The experimental data are further applied to validate the FE modeling of the test vehicles, which are shown in Fig. 8(b) and Fig. 15. Strain/stress of the PP-WLCSP. (a) von Mises stress. (b) Equivalent plastic strain. (d), respectively. The material properties associated with these two test vehicles are shown in Table I. Based on the modified Coffin-Manson relationship, the prediction of the fatigue life of solder joints requires the corresponding strain information; however, in a nonlinear FE analysis, an extremely mesh-sensitive strain concentration field would be induced at the corners of solder joints due to their significant geometry/material change. In this study, the strain within a finite zone around the corner of the most critical solder joint in reliability is averaged by using a finite-volume-weighted averaging technique [12]. The averaged strain is then applied for further assessment of solder joint reliability. Fig. 15 shows an example of the corresponding Von Mises stress and equivalent plastic strain distributions in solder joints of the PP-WLCSP. The modeled solder joint fatigue life associated with these two WLCSP designs is shown in Table III also, in which it is 425 cycles for the PP-WLCSP and 225 cycles for the C-WLCSP. It is found that the prediction of numerical modeling correlates quite well with that of the experimental testing with the solution gap ranging from 20% 25%. Furthermore, FE modeling also indicates that the first possible failure

8 124 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 1, MARCH 2005 TABLE IV MODELED PLASTIC STRAIN AND THE ASSOCIATED PREDICTED SOLDER JOINT FATIGUE LIFE would occur at the edge of the outmost solder joint and in the interface between the solder joint and the bonding copper pad at the die side. This is exactly the same site where the interface cracking takes place during the ATC testing. With the above evidences, the appropriateness of the proposed FE modeling as well as the applied empirical fatigue life correlation model is extensively confirmed. The FE modeling of the solder joint fatigue life of the CP-WLCSP, PP-WLCSP, and DPS-WLCSP subjected to an ATC loading can then be performed. It is special to note that the thermal cycling loading in the numerical ATC testing is different from that of the experiment one, as mentioned previously. In the simulations, the polymer post height in the PP-WLCSP, the copper post height in the CP-WLCSP and the double-pad structure height in the DPS-WLCSP are all 40 m. The maximum averaged equivalent plastic strain range and the associated fatigue life are shown in Table IV. It is found that for these types of WLCSP, the maximum averaged equivalent plastic strain all occurs in the interface between the solder joint with the maximum DNP and the attached pad at the die side. This implies that the failure mechanism does not shift to other locations for these WLCSP designs. Besides, the location is exactly the same as the cracking site in the fatigued solder joint of the PP-WLCP and C-WLCSP under an experimental ATC testing, shown in Fig. 14. Table IV also shows that under the same stress buffer layer thickness, the DPS-WLCSP is superior to both the PP-WLCSP and CP-WLCSP. It should be noted that the solder joint reliability of the C-WLCSP could be accordingly enhanced if the thickness of the stress buffer layer can be multiplied. Unfortunately, from the material and manufacturing process point of view, there present considerable difficulties. C. Effect of the Thickness of the Second Buffer Layer In order to explore the effect of the thickness of the stress buffer layer on solder joint reliability, the thickness of the second stress buffer layer varies from 35 to 75 m while that of the first stress buffer layer remains unchanged, which is 5 m. In other words, the post/column height associated with the CP-WLCSP, PP-WLCSP, and DPS-WLCSP is also changed accordingly. The results are shown in Fig. 16. It shows that the thermal fatigue life of solder joints increases as the thickness of the stress buffer layer or the height of the post/column height increases. Regardless of the thickness of the stress buffer layer, the proposed novel WLCSP design indeed outperforms the other types. Basically, the thermal fatigue life is nearly linearly proportional to the buffer height. Unlike the conventional WLCSP, the buffer height in the novel DPS design could be easily doubled, and accordingly, the enhancement of the corresponding solder joint fatigue life is facilitated. Furthermore, it is observed that the fatigue life of the DPS-WLCSP could nearly attain 1000 thermal cycles as the thickness of the second stress buffer reaches 75 m. Fig. 16. Comparison of solder joint fatigue life among these three types of WLCSP. Fig. 17. DPS design associated with a variety of copper columns. (a) Case I. (b) Case II. (c) Case III. (d) Case IV. Fig. 16 also demonstrates that the PP-WLCSP slightly surpasses the CP-WLCSP in solder joint reliability throughout the variation of the stress buffer layer thickness even though the improvement is not very significant because of the use of a thick copper overcoat in the polymer posts. D. Effect of the Distributing Layout and Number of Copper Columns The investigation involves two designs: 1) the number of copper columns and 2) the distributing layout of these copper columns. The dependence of these two design parameters on the solder joint reliability of the DPS-WLCSP is studied. Note that copper columns are in a round shape with a diameter 30 m. In the design, four modeling sub-cases are performed, each of which corresponds to a different number of copper columns, including 1, 3, 3, and 5, respectively. The distributing layout of copper columns associated with these sub-cases are shown in Fig. 17, in which the only difference between Case II and Case III is the way of distribution of copper columns. The parametric results are shown in Fig. 18, associated with the thickness of stress buffer layer. It is observed that the DPS associated with one copper column provides the best solder joint reliability among these four models, and the corresponding fatigue life exceeds 1000 thermal cycles. In addition, an increase of copper columns would lower the solder joint reliability. However, it should be noted that during manufacturing process, an excessively small number may easily result in the damage of these copper columns and is also difficult to construct the second copper pad. Furthermore, as can be observed in Fig. 18, the number of copper columns would have a greater impact on

9 LIN et al.: DESIGN AND ANALYSIS OF WAFER-LEVEL CSP WITH A DOUBLE-PAD STRUCTURE 125 Fig. 18. DPS. Effect of the distributing layout and number of copper columns in the Fig. 20. Effect of the diameter of copper columns in the DPS. VII. CONCLUSION Fig. 19. DPS design associated with a different diameter of copper columns. (a) Case I. (b) Case II. (c) Case III. (d) Case IV. solder joint reliability as the buffer layer thickness becomes thicker. By comparing the results of Case II with those of Case III, a horizontal alignment of these three copper columns provides a better solder joint fatigue life than a vertical alignment, demonstrating the effect of the distributing layout of copper columns on solder joint reliability. E. Effect of the Diameter of Copper Columns It should be noted that under WL manufacturing process, it is difficult to construct an excessively slender copper column using photolithography process. It is therefore suggested that the diameter of the copper columns should be between m. In order to examine the dependence of the solder joint reliability of the DPS-WLCSP on the diameter of copper columns, two different DPS designs, shown in Fig. 19, are used in the parametric analysis. The first design is the DPS associated with only one copper column and the second design is that corresponding to five copper columns. For each design, the investigation involves two sub-designs, each of which is composed of a different column diameter. The diameter of the copper columns associated with these two sub-design is 30 m and 60 m, respectively. The results are shown in Fig. 20. The fatigue life data are plotted with respect to the buffer layer height. It is found that the larger the copper columns, the less the solder joint reliability despite of the number of copper columns applied in the DPS. In addition, the effect of the design parameter becomes much more substantial as the number of copper columns or the buffer layer thickness increases. A novel WLCSP with a DPS is proposed in this research. In order to substantiate the feasibility of the DPS-WLCSP in solder joint reliability enhancement, three different other types of WLCSP, including the C-WLCSP, the PP-WLCSP, and the CP-WLCSP, are considered in the investigation. A 3-D nonlinear FE modeling technique together with the modified Coffin Manson relationship is employed in this study to numerically assess the solder joint reliability of these WLCSP under JEDEC thermal cycling specifications. The validity of the FE modeling is extensively confirmed through Twyman Green interferometry measurement and an experimental ATC testing. The FE results show that the critical strain location associated with these four WLCSP designs is identical, and more importantly, coincides with the cracking site in the fatigued solder joint of the PP-WLCP under the experimental ATC testing. It is obvious that with an appropriate design of the DPS, the DPS-WLCSP can hold good structural compliance and thus, provide enhanced solder joint reliability. It is found that under the same stress buffer layer height, the new design could outperform other advanced WLCSP designs, such as the PP-WLCSP and CP-WLCSP packages. Even though the manufacturing cost of the new design would be slightly higher than the standard one, it is relative less expansive than some other advanced designs. In addition, unlike the limited stress buffer layer height in a conventional WLCSP design, the copper column height can be easily enhanced to achieve higher solder joint reliability. The modeled results show that as the buffer layer thickness goes beyond 75 m, the board level solder joint reliability of the DPS-WLCSP could pass the industry expectation of 1000 cycles of thermal cycling for computer applications, such as desktops, laptops and workstations. The parametric design of the DPS also shows that a less number of copper columns with a higher column height and a smaller cross-sectional area would provide better solder joint reliability, and the distributing layout of these copper columns presents a certain impact on the solder joint fatigue life as well. Based on the above evidence, it is concluded that the proposed DPS-WLCSP provides a very promising, alternative solution for enhancing the solder joint reliability of

10 126 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 28, NO. 1, MARCH 2005 WLCSP, and more importantly, is feasible and cost effective because of conforming to the standard WL manufacturing process. REFERENCES [1] P. Elenius, S. Barrett, and T. Goodman, Ultra CSP wafer level package, IEEE Trans. Compon. Packag. Technol., vol. 23, no. 2, pp , May [2] Y. T. Lin, C. T. Peng, and K. N. Chiang, Parametric design and reliability analysis of wire interconnect technology wafer level packaging, ASME Trans. J. Electron. Packag., vol. 124, pp. 1 6, Sep [3] T. Kawahara, SuperCSP, IEEE Trans. Compon. Packag. Technol., vol. 23, no. 2, pp , May [4] P. Garrou, Wafer level chip scale packaging (WL-CSP): An overview, IEEE Trans. Adv. Packag., vol. 23, no. 2, pp , May [5] T. DiSteffano, Wafer level fabrication of IC packages, Chip Scale Rev., p. 20, May [6] M. S. Bakir et al., Sea of leads ultra high-density compliant wafer-level packaging technology, in Proc. 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IEEE 40th Electronic Components Technology Conf., Las Vegas, NV, 1990, pp [20] M. Pecht et al., To cut or not to cut: A thermal-mechanical stress analysis of polyimide thin-film on ceramic structures, IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 18, no. 1, pp , Feb [21] D. Post, B. Han, and P. Ifju, High Sensitivity Moiré: Experimental Analysis for Mechanics and Materials. New York: Springer-Verlag, [22] Temperature Cycling, JEDEC Std. JESD22-A104-B, Jul [23] K. C. Kapur and L. R. Lamberson, Reliability in Engineering Design. New York: Wiley, Ji-Cheng Lin received the Ph.D. degree in mechanics from National Tsing Hua University, Hsinchu, Taiwan, R.O.C., in His research was focused on wafer-level packaging and semiconductor sensor design. He has contributed to various projects related to electronic packaging and semiconductor sensor including simulation/reliability test and wafer level stress-strain/temperature measurement. He is currently working for Delta Electronics, Taipei, Taiwan, in the areas of projection system product design. He has one U.S. and three Taiwan patents on pressure sensor and wafer-level packaging. Hsien-Chie Cheng (M 01) received the B.S. degree in civil engineering from National Cheng Kung University (NCKU), Tainan, Taiwan, R.O.C, in 1985, and the Ph.D. degree in applied mechanics from the University of Michigan, Ann Arbor, in He is Associate Professor of Aerospace and System Engineering at Feng Chia University (FCU), Taichung, Taiwan. Prior to FCU, in 1994, he joined the R&D Division, National Center for High-Performance Computing (NCHC), Taiwan, as an Associate Research Scientist, and in 1998, became the leader of the Computational Solid Mechanics Laboratory, NCHC. He has published more than 60 conference/journal papers in the areas of CAE, structural optimization, and electronic packaging. His current main research activities are focused on thermal management, design optimization, thermal-mechanical analysis, and solder joint reliability of advanced packaging, including 3-D stacked MCM, wafer-level CSP, and MEMS packaging. Dr. Cheng is a Member of ASME. Kuo-Ning Chiang received the Ph.D. degree in mechanical engineering from the Georgia Institute of Technology, Atlanta. He has published more than 100 journal/conference papers in the area of computational solid mechanics, electronic/optical packaging, MEMS, and nano-technology. He has frequently organized, and served as a technical committee and session chair in the international conferences. He was responsible for more than 40 electronic packaging/mems projects that related to solder reflow, package simulation/design, sensor/nano-structure design and reliability analysis of electronic/mems devices. He holds three U.S. and 18 Taiwan Electronic Packaging Device Patents, and has six U.S. and eleven Taiwan Electronic Packaging/Optical Device patents pending. Dr. Chiang received the Outstanding Paper Award from two journals, the Outstanding Teaching Award from the Engineering College of the National Tsing Hua University, the Outstanding Research Award from his Department, three times, and the Distinguished Research Award from the National Science Council of Taiwan (the Taiwan equivalent of the National Science Foundation). He is a Fellow of ASME.