Resistive switching of CeO x /SiO 2 stacked film based on anodic oxidation and breakdown

Transcription

1 Feb. 19 th, 2015 WIMNACT-45 Resistive switching of /SiO 2 stacked film based on anodic oxidation and breakdown K. Kakushima Tokyo Institute of Technology 1

2 Introduction to resistive RAM (RRAM) Reset OFF State Advantage Metal High Resistance Metal Two terminal device nonvolatile fast switching (<100ns) Set Metal Low Resistance Metal ON State large volume compatible with BEOL Fast switching speed to replace DRAM 2

3 Basic operation of resistive RAM (RRAM) Top Electrode Oxide Bottom electrode Forming process ON-state(LRS) TE BE Oxygen vacancies reset set OFF state(hrs) TE BE Forming process: Creation of oxygen defect chains for electron conduction W/CeO 2 /TiN Set/Reset mechanism: Oxygen compensation at the tip of filament to change the electron conductivity Control of filament is the key for switching Elimination of forming process 3

4 3D stacking of RRAM with cost reduction I. G. Baek, IEDM 2011 J. D. Choi, VLSI 2011 RRAM with large volume is possible with the analogy of 3DNAND structure 4

5 Reported materials for RRAM Selection from compatibility with CMOS process Nice endurance, ON/OFF ratio of <100 5

6 Latency gap between DRAM and NAND D. Wouters, SISC 2012 Large speed gap between DRAM and flash Additional memory (storage class memory) is needed to fill this gap Requirements nonvolatile switching speed of ~100ns large capacity (large ON/OFF ratio) RRAM should have large ON/OFF ratio for storage class memory application 6

7 Issues of RRAM for storage class memory A. Chen, APL, 2000 R ON depends on current limit Still, only ratio increase by x10 Resistanceratio Storage Class Memory Flash Memory Atomic switching ReRAM PRAM MRAM Operation speed (ns) ON/OFF ratio comparable to flash with stable and low ON resistance should be achieved Forming-free desirable 7

8 Selectors for RRAM LRS LRS 1T1R (6F 2 ) Large ON/OFF ratio High temp. process for Tr. LRS HRS 1D1R (4F 2 ) Large ON/OFF required 3D integration possible Oxide based, organic based pn junction reported, so far I. G. Baek, IEDM 2005 More easy to use Si based Zener diode Our target is based on condtion to use Si-based diodes 8

9 Outline of the presentation 1. Introduction 2. Proposal of RRAM based on local breakdown and anodic oxidation 3. /SiO 2 stacking on Si bottom electrodes 4. /SiO 2 on NiSi 2 bottom electrodes 5. Conclusions 9

10 Basic operation of proposed RRAM SET: R HRS R LRS RESET: R LRS R HRS Local breakdown for set process Anodic re-oxidation to recover the spot for reset process 10

11 Analytical model for set voltage (V set ) t high-k t low-k V = = t t = t Top electrode High-k Low-k Bottom electrode E low k low k + low k Elow k + low k + t t t high k k high-k k low-k high k high k k k E k k low k high k high k low-k high-k E +V E high-k E low-k E 0V low k low k V set (V) V set = t k high-k = t high-k (nm) low k + t t SiO2 =3nm t SiO2 =2nm t SiO2 =1nm BD ESiO 2 high k SiO 2 as a low-k film k high-k =28 k k t SiO2 =3nm t SiO2 =2nm t SiO2 =1nm =14MV/cm low k high k E low k BD Large contrast in k-value is effective in reducing the V set 11

12 Resistance at LRS (R LRS ) and HRS (R HRS ) Top Electrode (TE) High-k R LRS = R high-k + R B.D. spot Low-k R HRS = R high-k + R low-k Bottom Electrode (BE) Requirements for lower R LRS and higher R HRS High electron conductivity High-k Narrow bandgap with low energy band layer offset in CB at interface low-k layer Low k-value Wide bandgap with large CB band offset 12

13 Material selection for high-k and low-k Low-k J. Robertson, JVSTB High-k A strong candidate for set process as high-k layer SiO 2 as low-k layer 13

14 Material property for reset process 0V -V Top electrode SiO 2 Bottom electrode R. Gerhardt-Anderson, et al., Solid State Ionics, 5, (1981). S. Thevuthasan, et al., 3rd IEEE-NANO, pp (2003). High-k layer should have high oxygen ion conduction at room temperature 14

15 Impact of low-k layer thickness for RRAM Oxygen Ionic conductivity (S/cm) 10-9 ON forming ON set LRS initial reset reset set OFF Forming-free region OFF Thickness of low-k (nm) High-k with high s ox High-k with moderate s ox Too thick low-k layer needs large forming voltage Higher oxygen ionic conductivity for high-k layer can provide forming-free switching 15

16 SiO 2 layer formation with Deposition at 300 o C HF treatment Si (100) W SiO 2 (~1nm) Si (100) W Si (100) Thin SiO 2 layer is automatically formed at /Si substrate interface even at as-deposited sample 16

17 Oxidation of Si with Intensity (a.u.) Intensity (a.u.) Ce Ce before annealing Ce 3d 5/2 Ce 3+ Ce-silicate + msi + + Ce-silicate Ce 4+ ysi Binding energy (ev) after annealing at 500 o C Ce 3d 5/2 Ce-silicate Ce 3+ Ce-silicate Ce 4+ Ce 3+ n n Binding energy (ev) 1 2 O O ( 4+ Ce ) yce Ce 2 O 3 CeO 2 silicate Ce 3+ 47% 19% 34% annealing Ce 2 O 3 CeO 2 silicate 26% 26% 48% 3+ xce + (1 3+ silicate y)ce 4+ + (1 + ysio x=0.34, y=0.74 x)ce Extract Ce 3+, Ce 4+ and silicates from Ce3d 5/2 spectra -Silicates and SiO 2 from Si1s spectra - forms silicates rather than SiO 2 -x and y should be extracted for oxides with valence number fluctuation 17

18 Outline of the presentation 1. Introduction 2. Proposal of RRAM based on local breakdown and anodic oxidation 3. /SiO 2 stacking on Si bottom electrodes 4. /SiO 2 on NiSi 2 bottom electrodes 5. Conclusions 18

19 Sample preparation of /SiO 2 stack Top electrode (TE): W Bottom electrode (BE): p + Si (assuming Zener diode) p + -Si substrate (10 18 cm -3 ) SPM&HF cleaning evaporation at 300 o C Top electrode (W) deposition Metal etching by RIE Backside contact (Al) formation 20 µm W p + -Si sub Al Measurement 19

20 Polarity for resistive switching rd 3 rd 4 th Current(A) st 2 nd 2 nd 1 st W/ W/ IL/p + -Si IL/p + -Si Voltage(V) Voltage(V) Resistive switching only observed for counter clockwise Might be the effect of oxygen ions with negative charges 20

21 RTO process for SiO 2 formation Top electrode (TE): W Bottom electrode (BE): p + Si p + -Si substrate (10 18 cm -3 ) SPM&HF cleaning 5%O 2, 850 o C, 5min evaporation at 300 o C Top electrode (W) deposition Metal etching by RIE Backside contact (Al) formation 20 µm W SiO 2 p + -Si sub Al Measurement 21

22 Impact of RTO-SiO 2 layer on ON/OFF ratio Current (A) (a) 2 nd 3 rd Voltage (V) CC: 1mA CC: 100µA 1 st /RTO/p + -Si /IL/p + -Si ((b) (c) p + -Si p + -Si forming (large CC) forming (small CC) reset set reset set O 2- O 2- O 2- O 2- With RTO-SiO 2, lower current limit, lager ON/OFF ratio from 10 3 to 10 4, owing to background leakage current suppression 22

23 p + Si and n + Si as bottom electrodes Current (A) Current (A) (a) p + -Si BE (b) n + -Si BE V reset 2nd, 3rd, 10th, 20th, 30th, 40th, 50th, 60th, 70th, 80th, 90th, 100th p + Si BE V reset 2nd, 3rd, 10th, 20th, 30th, 40th, 50th, 60th, 70th, 80th, 90th, 100th n + Si BE 100times of operation V set forming (1 st sweep) V set forming (1 st sweep) Voltage (V) Frequency Reset: -5V (sweep) p + -Si BE < ~ ~ ~ ~ ~ ~ ~ ~ ~ ~7.0 >7.0 V set (V) n + -Si BE With n + Si BE, shift in V set of 1 V can be observed

24 Band diagram with p + Si and n + Si BE p + -Si SiO 2 p + -Si W E f n + -Si y E f n + -Si SiO 2 W E BD Workfuntion difference shifts the voltage for switching One of the supporting evidence for our model

25 Outline of the presentation 1. Introduction 2. Proposal of RRAM based on local breakdown and anodic oxidation 3. /SiO 2 stacking on Si bottom electrodes 4. /SiO 2 on NiSi 2 bottom electrodes 5. Conclusions 25

26 Materials for bottom electrodes Current (A) Compliance Current:1mA (a) W W Initial Reset Process Set Process Voltage (V) 10 Current (A) Compliance Current:0.75mA -10 (b) W Ti Initial Reset Process Set Process Voltage (V) Bad insulating property of interface layer for W, and Ti BE -> small ON/OFF ratio The resistance change is due to Change of interfacial layer resistance E CeOx E IL Current (A) W (c) W Ni Interfacial layer W, Ti, Ni Initial Reset Process Set Process Voltage (V) 10 Small Dielectric constrast between CeOx and NiO Switching Layer 26

27 with TiN bottom electrode 10-2 Compliance Current:2mA W Current (A) W TiN 10-8 Initial Reset Process Set Process Voltage (V) E CeOx E TiO2 TiN W TiO 2 TiN +V 0V TiO 2 Switching Layer Due to high k-value of TiO 2, becomes the switching layer (behavior is similar to conventional RRAM) Si based metal electrode is prefered 27

28 Stacked sputtering process Multi layered-deposition of Ni and Si layers No diffusion of Ni atoms into Si channels Ni case NiSi 2 case Consumption of Si from substrate is limited to the first Ni layer Complete suppression of lateral encroachment - Atomically flat interface can be achieved - Interface position can be well-defined - Applicable for scaled channel Stacked sputtering process is promising for electrodes for nano-scale devices 28

29 Silicide film stability on temperature (8sets of Si/Ni (total thickness of 10nm)) XPS measurement of silicide film Sheet resistance and surface roughness Intensity (a.u.) 857 hν= ev Ni2p 3/2 RTA : 1min in N 2 t Ni :3.0nm as depo t Ni :3.0nm 250 o C t Ni :5.5nm 500 o C t Ni :3.0nm 500 o C stack 500 o C Binding energy (ev) Ni Ni-rich NiSi NiSi ρ sh (Ω/sq.) Phase of the silicide is mainly NiSi Ni (5.5nm) wide process window stacked NiSi 2 agglomeration Ni (5.5nm) stacked NiSi NiSi Annealing temperature ( o C) Annealing temperature ( o C) NiSi 2 films with stacked silicidation process are resistant up to 900 o C annealing Roughness (nm) Wide process temperature window (350~900 o C) 29

30 /SiO 2 stack on NiSi 2 BE SiO 2 (100nm)/p + -Si substrate 20mm Metal (NiSi 2 ) deposition & anneal Annealing at 500ºC for 1min (N 2 ) Insulator ( ) evaporation at 300ºC Metal (W) deposition Metal etching Backside contact formation (Al) Al W NiSi 2 SiO 2 p + -Si Measurement 30

31 TEM image of /SiO 2 on NiSi 2 BE W SiO 2 (~1.5nm) NiSi 2 Smooth NiSi 2 BE with uniform 1.5nm-thick SiO 2 confirmed 31

32 Resistive switching with NiSi 2 BE 10-2 Compliance Current:2mA Current (A) (a) t CeOx =13nm Voltage (V) 10 Forming-free resistive switching can be obtained ON/OFF ratio over 10 5 is achieved 32

33 Switching with different thickness 10-2 Compliance Current:2mA 10-2 Compliance Current:2mA Current (A) Current (A) (a) Voltage (V) Compliance Current:5mA (c) t CeOx =13nm t CeOx =2nm Voltage (V) Current (A) Voltage (V) =1.5 (nm) =16 (MV/cm) Thickness dependency on V set can be modeled with breakdown model SET (b) (d) t CeOx =6.5nm 33

34 Resistance change with switching cycle Resistance (Ω) V ~10 3 X 6.5 nm 13 nm OFF(HRS) ~10 3 X ON(LRS) # of switching cycles Stable memory operation can be obtained 34

35 Effect of additional annealing for NiSi 2 Current (A) Current (A) Compliance Current:2mA (a) Compliance Current:100µA (c) NiSi 2 without annealing Voltage (V) NiSi 2 with 650 o C annealing in 5%O Voltage (V) Current (A) Current compliance (ma) Compliance Current:1mA (b) NiSi 2 with 500 o C annealing in 5%O Voltage (V) (d) w/o anneal ON/OFF ratio over 10 6 can be obtained with surface oxidation of NiSi o C in N o C in O o C in O HRS/LRS ratio

36 Conclusions Resistive switching device for storage class memory application based on local breakdown and anodic oxidation is proposed and a guideline for material selection has been presented Stacking of and SiO 2 has shown switching characteristics base on our model Quality of SiO 2 layer is the key to increase the ON/OFF ratio With NiSi 2 bottom electrode, forming-free switching with ratio of 10 8 has been achived 36