Electron Beam Lithography patterned Hydrogen Silsesquioxane (HSQ) resist as a mandrel for Self- Aligned Double Patterning application

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1 Electron Beam Lithography patterned Hydrogen Silsesquioxane (HSQ) resist as a mandrel for Self- Aligned Double Patterning application Running title: EBL patterned HSQ resist as a mandrel for SADP application Running Authors: Desai et al. Vishal U. Desai, John G. Hartley, Nathaniel C. Cady a) Colleges of Nanoscale science and Engineering (CNSE), SUNY Polytechnic Institute, 257 Fuller Road, Albany, NY a) Electronic mail: ncady@sunypoly.edu The semiconductor industry has developed various alternative approaches for obtaining high resolution patterns (sub-30 nm) using existing lithography techniques. Of the alternative approaches, Self-Aligned Double Patterning (SADP) is the approach which involves the fewest lithography steps. In SADP a dummy pattern, also known as a mandrel, is first formed, followed by a conformal spacer material deposited on the patterned mandrel. Using dry reactive ion etching (RIE), spacer sidewalls are then formed. In the final step the mandrel is removed by an etch process. The result is the double pattern of the spacer material. The advantage of this approach is that only one lithography step with the critical dimension (CD) of the double patterns is defined by the deposited spacer thickness. The disadvantage is the requirement of multiple, successive deposition and etch processes. In the present research, we demonstrate a reduction in required processing steps by using a novel mandrel/spacer approach for the SADP scheme. Using electron beam lithographically (EBL) patterned HSQ resist and plasma enhanced chemical vapor deposition (PECVD) deposited low stress silicon nitride, we demonstrate a proof of concept of the SADP patterning scheme with reduced process steps. 1

2 I. INTRODUCTION Double patterning is one of the scaling approaches which is used to double the density of originally patterned lines. The various double patterning approaches are Litho-Etch- Litho-Etch (LELE), Litho-Freeze-Litho-Etch (LFLE) and Self-Aligned Double- Patterning (SADP) 1. The LELE and LFLE are approaches where the double patterns are obtained by using two lithography steps. These two approaches introduce the potential source of an overlay error, which is the result of position misalignment between two exposed patterns. The SADP approach needs only one lithography step 2,3. The double patterns in SADP are created by processing various deposition and etch steps on the initially created lines. The spacer thickness is determined based on the target width of the doubled pattern. The SADP approach eliminates the source of overlay error which can occur when using either LELE or LFLE approaches. Furthermore, SADP relaxes both resolution and image placement. On the other end, there are more processing steps using SADP approach as compared to the LELE and LFLE approach. In the conventional approach, the substrate is protected from etching during spacer RIE by either a dielectric or hard mask material. Initial patterns are formed in a resist layer. The spacer material is then deposited either on the resist mandrel or on the patterntransfer layer (hard mask). Moreover, based on the lithography process, there may be the need to deposit additional thin film layers beneath the resist 4. The spacer conformal deposition is performed by either a chemical vapor deposition (CVD) or an atomic layer deposition (ALD) process. The dielectric spacer deposition using LPCVD (low-pressure chemical vapor deposition) is performed at a higher temperature ( C) 5. The higher temperature deposition chamber for LPCVD requires a longer time to ramp up and 2

3 down and subsequently increases the total processing time. ALD yields highly conformal films but being the slower process takes very long to deposit several hundreds of nanometers of film 6. In summary, the large number of pattern transfer steps (including the resist, hard mask and deposited layers) increases the overall number of processing steps and therefore total process time. Electron beam lithography (EBL) currently provides the highest patterning resolution 7,8 for patterning semiconductor devices, as the resolution is not limited by the wavelength of light. Moreover, EBL systems do not require masks for patterning. This provides flexibility for trying various patterning schemes for process development in a very short time. Low throughput is the main drawback which restrict the use of EBL for high volume manufacturing. The present work utilizes the general SADP approach while reducing the total number of processing steps. The initial resist mandrel is formed using hydrogen silsesquioxane (HSQ) resist on the silicon substrate. This is a negative tone electron beam resist which converts to a predominantly silicon oxide material after e-beam exposure 9. As a result, the dry and wet etch recipes to etch silicon oxide can also be applied to the patterned HSQ resist. Furthermore, no under layers are deposited beneath the resist. Figure 1A depicts the conventional process flow showing various process steps as compared with our developed process flow as shown in Figure 1B. 3

4 Figure 1: (Color online) Comparison of the process flow of conventional SADP approach vs our novel approach. (A) The conventional approach has additional process steps at deposition and at the pattern transfer level. These steps include 1) patterning stack with hard mask, 2) resist patterning, 3) pattern transfer, 4) resist removal, 5) spacer deposition, 6) etch to create spacer sidewall, and 7) etch to remove hard mask. (B) The approach used in this work utilizes HSQ resist without any hard mask reduces process steps at deposition and pattern transfer level. This approach uses only five steps, including 1) HSQ deposition, 2) HSQ patterning, 3) spacer deposition, 4) etch to create spacer sidewall, and 5) etch to remove HSQ. II. EXPERIMENTAL A Vistec VB300 electron beam lithography tool operating at 100 KV was used for patterning HSQ resist (XR-1541) from Dow Corning at the SUNY Polytechnic Institute College of Nanoscale Sciennce & Engineering (CNSE). The resist was spin coated on 3-4

5 inch (75 mm) Silicon Wafer with the thickness of about 190 nm ± 10 nm. The patterned linewidth to pitch ratio was 1:3. The patterned wafer was developed in 2.38% tetramethyl ammonium hydroxide based solution for 2 min followed by a DI water rinse. In the present work the target lithography patterns were 240 nm lines on a 720 nm pitch. This approach was aimed to develop the process where the low-resolution patterns are used as a mandrel which then can be scaled down to higher resolution patterns through either double or multiple patterning. Silicon nitride was used as the spacer and was deposited using plasma enhanced chemical vapor deposition (PECVD). The major advantage of using PECVD is the lower deposition temperature ( C) compared to the conventional LPCVD process ( C). Note that the PECVD deposited silicon nitride can be represented as SiN x H y. PECVD Spacer deposition was performed using a Plasmatherm 73/74 Dual Chamber PECVD/RIE plasma system. Depositions were performed at the Micro and Nano Fabrication Clean Room (MNCR) at Rensselaer Polytechnic Institute. Silane and Nitrogen were the gases used for the deposition. Moreover, for using the spacer with lower film stress, helium dilution was used 10. Plasmatherm s VERSALOCK Inductively Coupled Plasma (ICP)-Reactive Ion Etching (RIE) tool was used for etching spacer at CNSE. CHF 3 (Fluoroform) and O 2 (Oxygen) were the etch gases used 11. The HSQ resist mandrel was wet etched using the buffered HF improved, a ready to use solution from Transene Company, Inc. The etching was performed by immersing the sample in etching solution at room temperature. A Solaris 150 Rapid Thermal Processing system from Surface Science Integration (SSI) was used for the Rapid Thermal Annealing (RTA) treatment of the spacer. 5

6 Scanning electron microscopy (SEM) micrographs were obtained using LEO-1550 and Hitachi-S4800 SEM at CNSE. Sample preparation for cross-section was performed by cleaving sample in the direction normal to the patterns using a diamond scribe. III. RESULTS This section discusses the results of silicon nitride as a spacer for the double patterning application. We investigated two types of PECVD based silicon nitrides: regular silicon nitride and low stress silicon nitride. Both materials were evaluated as a spacer. The deposition temperature for regular silicon nitride was 250 C while the low stress silicon nitride was deposited at 300 C. The deposition rates were higher for the regular silicon nitride (18 nm /min) as compared to the low stress silicon nitride (5 nm/min); however, low stress silicon nitride (LSSiN) has a relatively low etch rate in HF as compared to silicon oxide 12. A. Silicon Nitride as a spacer: The PECVD deposition of a silicon nitride spacer was performed at 250 C on a patterned HSQ resist mandrel. The target width of the double patterns were 120 nm and as a result, the deposited spacer thickness chosen to be 120 nm. 6

7 Figure 2: SEM images showing SADP process flow using silicon nitride as a spacer. (A) HSQ mandrel patterns on Si-substrate without any resist underlayers, (B) PECVD deposited silicon nitride spacer on HSQ patterns, (C) ICP-RIE of spacer creating opening in the mandrel, (D) buffered HF etch for HSQ mandrel removal. The etch parameters used for spacer etch were chamber pressure 7 mt, RIE power 100 W, ICP power 600 W, and the process time was 40 sec. The gas flow was 45 sccm of CHF3 and 5 sccm of O 2. As seen in the above Figure 2C, during the ICP-RIE of the silicon nitride the Si substrate was etched, as there is no etch stop material deposited to protect the substrate. The wet etch of patterned HSQ was performed for 30 sec. As shown in Figure 2D, silicon nitride demonstrated poor selectivity from the patterned HSQ mandrel. There were two problems that were identified from this experiment. One was the need to protect the Si substrate during the etching of spacer material and the second was to selectively remove the HSQ mandrel from the spacer sidewalls. As a result, LSSiN was examined as a spacer which was deposited using PECVD, as described in the following section. 7

8 B. Low Stress Silicon Nitride as a spacer: To reduce over-etch into the Si substrate and improve HSQ mandrel vs. spacer etch selectivity, LSSiN was explored as an alternative spacer to standard silicon nitride. Figure 3 the results when LSSiN was used as the spacer material. Figure 3: SEM images showing SADP process flow using LSSiN as a spacer, (A) PECVD deposited LSSiN spacer on HSQ patterns, (B) ICP-RIE of spacer shows an opening in the mandrel with over-etching into the Si substrate, (C) buffered HF etch of HSQ mandrel showing improved selectivity to LSSiN spacer as compared to SiN spacer. The process conditions for spacer etch were: chamber pressure 7 mt, RIE power 150 W, ICP power 600 W, and total process time of 40 sec. The gas flow was 45 sccm of CHF 3 and 5 sccm of O 2. The HSQ mandrel was removed in 30 sec buffered HF etch. As shown in Figure 3C, LSSiN provided better selectivity from the patterned HSQ resist. LSSiN sidewalls were observed on the substrate, as desired, but substrate protection during ICP- RIE still needed to be assessed. 8

9 C. Two-step Spacer Etch: The slow etch of LSSiN in buffered HF was used as an advantage. Instead of etching the spacer completely from the top of the mandrel during the spacer etch, there was some spacer left purposefully on the top of the mandrel. As a result, there was also some spacer left on the substrate. During the mandrel removal, the remaining spacer layer etched slowly, and once it completely etched from the top, the HSQ resist mandrel was completely removed preserving the LSSiN double patterns. Figure 4 shows results from varying the etch time for the first step of the spacer etch. Figure 4C shows the profile with remaining spacer on the top of mandrel and substrate. 9

10 Figure 4: ICP-RIE of LSSiN for decreasing etch times. (A) 40 sec etch showing overetch into Si substrate, (B) 30 sec etch showing reduced over-etch in Si substrate, and (C) 25 sec etch showing a thin cap of LSSiN remaining on the Si substrate and at the top of the mandrel. The profile observed in Figure 4C was introduced to the wet etch of HSQ resist mandrel. In order to remove the remaining spacer from the top of mandrel, the wet etch was performed for an increased duration of 2 min. Figure 5 illustrates the double pattern of the LSSiN that resulted after removal of the LSSiN from the top of the mandrel and substrate. 10

11 Figure 5: Implementation of two-step-spacer etch results in LSSiN double patterns, post HSQ mandrel removal. The line-width of double patterns is reduced due to partial etch of spacer. The use of the two-step spacer etch demonstrated that the substrate could be protected without needing to deposit any additional underlayers / etch stop layers. Moreover, the resulting double patterns of the LSSiN showed that, as compared to the regular SiN, LSSiN has better etch resistance in buffered HF. As expected, due to the partial etch of the LSSiN during buffered HF etching, there is a reduction in the width of the LSSiN; however, the etch resistance of the PECVD deposited silicon nitride films can be increased by thermally annealing the film. The PECVD silicon nitride (SiN x H y ) film has a significant hydrogen concentration due the lower deposition temperature. Thus, thermal annealing causes a reduction in the hydrogen concentration, and as result, the etch resistance of the PECVD deposited silicon nitride film increases 13. The section below discusses the results of the rapid temperature annealing on the LSSiN spacer. 11

12 D. Modifying etch resistance via RTA treatment of PECVD LSSiN The effect of rapid thermal annealing (RTA) on the PECVD deposited LSSiN spacer was studied as a means of increasing the etch resistance of LSSiN during the buffered HF etch of the HSQ hard mask / mandrel. LSSiN spacer showed some resistance to buffered HF etch, but etch resistance was not suffient, as mentioned above. In order to test for improved etch resistance via thermal annealing, the sample (post spacer etch) was subjected to RTA for the target temperature of 750 C for 30 sec. Post RTA treatment the sample was then etched for 2 min in buffered HF. As anticipated, due to the increased etch resistance of the LSSiN spacer, the HF could not etch the HSQ, since it was protected by the remaining LSSiN spacer that formed a cap over the HSQ mandrel. Figure 6 shows the resulting profile of the structure post buffered HF etch. Figure 6: Pattern profile after buffered HF etching on the LSSiN spacer. The increased etch resistance of the LSSiN post RTA treatment yielded enhanced etch resistance, but also prevented removal of the cap layer, preventing the buffered HF etch of the HSQ mandrel. 12

13 From the above result, it was concluded that while the etch resistance of the LSSiN post RTA (~750 C for 30sec) treatment is increased, the use of two step spacer etch is not a viable method for obtaining double patterns. In order to facilitate the application of RTA on the spacer for improved double patterning, an alternative approach was to create opening in the mandrel (as opposed to protecting the mandrel with LSSiN) while adjusting the spacer etch recipe such that the over-etch in the Si substrate was reduced. After the spacer etch, the sample could then be treated with RTA, followed by the wet etch for mandrel removal. This approach was tested, using the following spacer etch parameters: chamber pressure 7 mt, RIE power 80 W, ICP power 600 W, and process time of 31 sec. The gas flow was 45 sccm of CHF 3 and 5 sccm of O 2. This was followed by a RTA of 750 C for 30 sec. Lastly, the sample was wet etched in buffered HF for 45 sec. Figure 7 shows the results of this experiment. 13

14 Figure 7: SEM cross section of structures A) after the ICP-RIE of the LSSiN spacer which created an opening in the mandrel while having less over etching in Si substrate, and B) LSSiN double patterns post RTA treatment followed by buffered HF wet etch. As observed in the Figure 7A, the opening in the mandrel provided an opening for buffered HF to contact and etch HSQ. As a result, the increased etch resistance of the LSSiN resulted in an improved double pattern profile. The measured average linewidth of the profile in Figure 7B is 48.5 nm with the measured standard deviation of nm. Whereas the average width of profile post two step spacer etch in Figure 5 is 31.1 nm with the measured standard deviation of nm. 14

15 IV. DISCUSSION AND CONCLUSIONS The obtained results suggest that with the two step spacer etch of LSSiN the Si substrate can be protected without addition of an under-layer / etch stop to resist the spacer etch. Altogether, there is the reduction in the total number of process steps for SADP, including reduction of both deposition and etch steps; however, the use of a two step spacer etch causes the partial etch of the spacer, resulting in thinner sidewall profiles than targeted. As a future direction, utilizing a thicker spacer (to account for the partial loss of spacer) may provide the target thickness of double patterns post mandrel removal. The thermal annealing of the LSSiN spacer increased its etch resistance in buffered HF and improved the resulting feature profile. As a future direction, thermal annealing at even higher temperatures (~900 C) could be performed on the LSSiN spacer deposited on the HSQ mandrel, to assess further improvements in etch resistance. The process flow developed herein is based on relatively low-resolution EBL patterns. This work could subsequently be applied to higher resolution patterning, to yield ultra high resolution SADP with direct patterning of the hard mask / mandrel layer. Depending on the initial pattern dimensions and spacing, the resolution should be able to reach sub 20 nm patterns. As the thickness of the spacer will determine the width of the double pattern, the primary limiting factor for the resolution is how conformally the PECVD spacer is deposited onto the HSQ mandrel. Atomic layer deposition (ALD) provides the most conformal deposition and for the further enhancement in the resolution, depositing the spacer using ALD would be a preferred approach. Furthermore, since HSQ resist is 15

16 converted to silicon oxide, this direct patterning / SADP process flow could be applied to other silicon oxide based structures. In conclusion, we successfully demonstrated the use of EBL patterned HSQ resist as a mandrel for double patterning application using the SADP approach. Using the HSQ resist mandrel eliminates the need for a hard mask layer and hence reduces the number of process steps for the SADP approach. PECVD silicon nitride showed poor etch selectivity vs. patterned HSQ mandrel, whereas LSSiN demonstrated much better etch selectivity. These results demonstrate the advantage of using relatively lower deposition temperature (300 C) as compared to conventional LPCVD ( C). The novel HSQ mandrel and PECVD LSSiN spacer combination provided the proof-of-concept that without depositing any under layers, the substrate can be protected by the use of a twostep spacer etch. Although the obtained line-width of the LSSiN double pattern is below target, this approach provides proof-of-concept of using HSQ resist as a mandrel and LSSiN as a spacer. ACKNOWLEDGMENTS Authors would like to acknowledge NSF (Award Number ) for funding this project. Furthermore, authors would like to thank Mr. Bryant Collwill from RPI for assistance with PECVD deposition tool. Authors would also like to thank Dr. Natalya Tokranova from CNSE for the assistance with ICP-RIE tool. 16

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