Microelectronic Device Instructional Laboratory. Table of Contents

Transcription

1 Introduction Process Overview Microelectronic Device Instructional Laboratory Introduction Description Flowchart MOSFET Development Process Description Process Steps Cleaning Solvent Cleaning Photo Lithography Introduction to Photolithography Photoresist Application Photoresist Spinner General Alignment Procedure Karl Suss Mask Aligner Quintel Mask Aligner Plasma Etching/Ashing Tegal Plasmaline 100 Oxygen Asher Chemical Etching SiO 2 Etching by Aqueous Methods Thermal Oxidation Oxidation Anneal Procedure Metallization CHA Electron Beam Evaporator Characterization Tencor Alphastep Profilometer Sheet Resistance Measurement HP 4145B Parametric Analyzer - N-MOSFET - PN Diode Tektronix Curve Tracer - TLM Table of Contents

2 - Resistors HP 4162 C-V Measurement - Capacitors

3 Introduction Semiconductors pervade our lives, from the personal computers on our desks and in our homes, to the microchips that control our car s engine. Since the invent of the semiconductor in 1956, development of semiconductor materials and devices has grown at an amazing pace. Semiconductor materials and devices is a $?? Billion industry. Developing semiconductor devices involves many steps, building layers on top of other layers, and removing portions of layers that are not wanted. Even a simple MOSFET device requires three separate oxidation steps, a doping step, four etch steps, two metallization steps, several photolithography steps, and countless additional steps such as annealing, cleaning and ashing. Description The Microelectronic Device Instructional Laboratory was established to give engineering students the opportunity to learn the fundamental basis of semiconductor processing, and the methods used to develop semiconductor devices. Each of the processes mentioned above are presented in detail in a classroom setting. The students then have ten (10) weeks of instruction in USC s Powell Instructional Laboratory, class 100 clean room to learn processes used to develop today s semiconductor devices. Beginning with a basic silicon wafer, students will build several devices typically found in today s microelectronics devices, including simple characterization devices such as Kelvin, Van der Pauw, TLM and resistors. Additionally, students will build more sophisticated devices such as PN diodes, capacitors, and MOSFET, the foundation of today s microprocessors. Flowchart The following flowchart and figures illustrate the process flow utilized in building N-MOSFET devices. p-type Si wafer Oxidation I Photolithography I Etch I Strip and Clean

4 Doping, n-type Oxidation II Photolithography II Etch II Strip and Clean Oxidation III Photolithography III Etch III Strip and Clean Photolithography IV

5 Metallization I Lift-Off Procedure Metallization II Anneal/Sinter n-type channel Source Drain Gate Top View of n-mosfet

6 MOSFET Development Process Description Week 1: Thermal Oxidation I Purpose - Thermal oxidation is performed to create a layer of oxide to be used for ion implantation masking, and as an insulating layer for device construction. The wafer is solvent-cleaned, rinsed with D.I. water and dried with N 2. The oxidation is performed in a Thermco 6 quartz tube furnace. The temperature is ramped to 1100 o C while flowing O 2. At 1100 o C, the O 2 is routed through a water bubbler held at ~96 o C. The exhaust of the bubbler is then routed in to the furnace to supply a partial pressure of water vapor to the atmosphere for wet oxidation. The temperature is held at 1100 o C for approximately 45 minutes under wet O 2 conditions. Then the O 2 is routed around the bubbler to supply dry O 2, and the temperature is then ramped down to a reasonable temperature for wafer removal. In accordance with the Deal-Grove model for silicon oxidation, this oxidation step results in a SiO 2 layer approximately nm thick. Week 2: Mask 1, n-type dopant Purpose To create a pattern of openings in the SiO 2,exposing the underlying Si, for ion implantation of n- type dopant. As seen in the drawings above, the source and drain regions of the MOSFET must be doped with n-type dopant. In order for the dopant to reach the Si regions, windows must be opened in the SiO 2 layer, to expose the underlying Si. This is accomplished with a photolithography step, followed by etching of the SiO 2. The photoresist used is AZ5214E-IR, by American Hoescht Celanese. It is a positive imaging photoresist with the ability to be used in an image reversal mode. The photolithography step is similar for all masks, except for the final metallization mask. The wafers are cleaned per the standard procedure. They then are placed on a wafer spinner. While spinning the wafer at 4000 rpm, an adhesion promoter, HMDS (Hexamethyldisilazane) is dropped on to the center of the wafer, 3-4 drops, one at a time. The centrifugal force distributes the HMDS outward toward the edge of the wafer, creating a thin uniform coating. Photoresist is then applied to the wafer while stationary. Then the wafer is again spun at 4000 rpm for 30 seconds to distribute the photoresist evenly across the wafer. The resulting photoresist layer is approximately 1.7 µm thick. The photoresist is dried on a hotplate at 120 o C for 2 minutes. The wafer is then aligned in the Quintel mask aligner, and exposed to a high intensity UV (365 nm) source. The mask that is loaded in the aligner provides a pattern to be transferred to the wafer by allowing light to reach some areas of the wafer and overlying photoresist, while blocking other areas. As this is a positive photoresist process, the photoresist in the exposed regions goes through a chemical change, and becomes highly soluble in specificallydesigned developer. Following exposure, the photoresist pattern is developed, using AZ400K (1:4) developer, for seconds, until the pattern just becomes clear, and photoresist can no longer be seen in the removed regions. The wafer is rinsed in D.I. water, dried and placed in the Tegal plasma asher. The RF plasma ashing is performed in a parallel plate asher, under vacuum, with a partial pressure of oxygen. An example of the atmosphere used is 350 mtorr, with 50 sccm O 2 flowing, at a net forward power of 300 W, for 3 minutes. This removes nm of photoresist from the entire wafer, to remove

7 any remnants of PR that were not completely removed in the developing step in the regions that are expected to be clear of PR. Although this removes photoresist from the unexposed regions, the remaining photoresist in these regions is um thick, sufficient for etch protection. Following ashing, the wafers are post-baked 5 minutes at 120 o C to harden the PR to reduce its solubility in the oxide etch. The wafers are then etched in a bath of buffered hydrofluoric acid, 7:1. The etch is performed for minutes to remove the approximate nm of oxide. The wafers are rinsed in D.I. water to remove the HF, and the PR is then stripped with Acetone, Methanol and water, and dried. Before continuing processing, to ensure that all PR is removed, the wafers are RF plasma ashed for 10 minutes at mtorr, with 50 sccm O 2 and 300 W net forward power. Week 3: Doping, n-type (and drive in if spin-on is used) Purpose To introduce dopants in to the Si material to create n+ regions in the p-type Si wafer. Spin-On Dopant The wafers are cleaned per the standard procedure. A dopant material is then applied to the wafer using the spin method. This spin-on dopant (SOD) is applied by dropping approximately 5-6 drops of phosphorosilicate liquid on to the center of each wafer, and then immediately spinning the wafer at 4000 rpm. This gives a uniform, nm thick layer of dopant-containing film on the wafer. The wafers are first dried on a hot plate for 5 minutes at 120 o C. The wafers are then loaded in to a quartz boat, and loaded in to the exhaust end of an 8 quartz tube furnace, which is held at approximately 800 o C. The temperature at the exhaust end of the tube furnace is measured to be approximately 300 o C, a sufficient temperature to pre-dry the SOD thin film. After fifteen (15) minutes, the wafers are introduced in to the center zone of the furnace, and the temperature ramped to 1100 o C while flowing O 2 and N 2 at approximately a 5% Oxygen concentration, and a total gas flow of 4 slm. After 15 minutes, the temperature is ramped down and the wafers removed from the tube furnace. Ion-Implantation The wafers are cleaned per the standard procedure. They are then loaded on to an ion implantation system and the ion implantation is performed at 50 KeV, and a dose of 1 x cm -1. Week 4: Doping Drive-in/activation (Non-SOD process) In the case of ion-implantation, the implanted regions are damaged due to the high energy ions bombarding the Si surface. Also, the dopant ions, typically As +, are lodged in high-energy, non-equilibrium positions in the Si lattice, and are not electrically active. Therefore, an annealing step must be performed to give the Si atoms and As ions enough energy to move in to equilibrium positions, thus repairing the damage cause by implantation. The wafers are cleaned per the standard procedure. They then loaded in to a quartz boat and introduced in to an 8 quartz tube furnace at 600 o C while flowing N 2. The tube furnace is ramped to 1100 o C, with N 2 flowing. At 1100 o C, the wafers are soaked for 5 minutes with the N 2 atmosphere, to allow the ions to move in to the wafer, and preventing them from being trapped in an oxide layer. After five minutes, the N 2 is turned off, and O 2 is flowed. After an additional 5-minute soak, the bubbler is opened, and wet O 2 flowed in to the tube furnace for 10 minutes. Following the wet oxidation, the bubbler is closed, and the furnace ramped down under a dry O 2 atmosphere, until the wafers are removed below 700 o C. Week 4: Mask 2, p-type dopant (SOD process)

8 In the case of diffusion of dopants from a SOD, an additional dopant step can be performed to introduce p- type dopants in appropriate regions in order to create pnp-type and CMOS devices. To accomplish this, a photolithography step must be performed to define regions for diffusion. Therefore, a photolithography step is done similar to the first lithography in week 2. Because of the added thickness due to the SOD thin film, additional time is required during the etch to expose the Si in the regions to be doped with p-type dopants. However, the oxide grown from the SOD is less dense than thermally grown oxide, and etches more rapidly in BOE. The wafers are stripped, dried and ashed for ten (10) minutes to ensure that no photoresist remains on the wafer surface. A dopant material is then applied to the wafer using the spin method, similar to week 3. The spin-on dopant (SOD) used for p-type doping is a borosilicate solution. Following its application and drying, the wafer is ramped to 1100 o C, and soaked for 5-10 minutes to diffuse the boron in to the exposed Si regions. The atmosphere of the tube furnace is again 5% O 2 in N 2, similar to the week 3 diffusion step. Week 6: Mask 3, gate oxide For the MOSFET devices, a thin (20-60 nm) gate oxide must be created between the source and drain regions. To accomplish this, the existing oxide in that region must be removed. Therefore, a photolithography step is performed, mask #3, followed by an oxide etch to remove the unwanted oxide in the gate regions. The photolithography and etch procedures have already been described above. Only the etch time is different to account for the increased oxide thickness due to two (2) SOD oxide layers. Week 7: Gate Oxidation The wafers are cleaned per the standard procedure. They are then placed in a quartz boat, and inserted in to a quartz tube furnace at approximately 700 o C with N 2 flowing. The temperature of the furnace is ramped to o C. At 800 o C, the N 2 is turned off, and O 2 flow is introduced into the furnace. At the specified temperature, o C, the wafers are soaked for minutes with the dry O 2 flowing. The furnace temperature is ramped down to < 700 o C, and the wafers removed. Week 8: Contact Via Definition Purpose Open vias to reach the n+ Si material in the source and drain regions for contacting. The wafers are cleaned per the standard procedure. A photolithography step is performed to define small openings on top of the oxide in the source and drain regions. The wafers are processed similar to the previous photolithography steps. In this step, it is crucial that the oxide in the vias is completely removed, to allow the metal contacts to reach the n+ material. Any thin oxide remaining will create a high resistance contact, and result in poor device electrical characteristics. Therefore, the wafers are slightly over-etched, approximately 2-4 um. The wafers are then rinsed, stripped, dried and ashed for 10 minutes. Week 9: Front-side metallization Purpose To deposit contact metal on the wafer front side using a liftoff procedure. A liftoff procedure is used to pattern the metal following deposition. This is accomplished by creating openings in a layer of photoresist where the metal (aluminum) is desired to stay. With the photoresist still on the wafer, the metal is deposited in a vacuum system. Following evaporation, the photoresist is stripped. During this strip procedure, the metal that is deposited on top of the photoresist is removed with the resist, while the metal that is deposited in the openings remains on the wafer. The wafers are cleaned per the standard procedure. The photoresist is then applied per the standard procedure. Following alignment and exposure, the wafers are reversal-baked for 1.5 minutes at 120 o C. This causes a chemical reaction to occur in the AZ-5214E-IR resist, re-linking the photoresist Novolak polymer in the exposed regions. It should be noted that during the exposure, the photosensitive material

9 (called DNQ) is mostly used up in the delinking reaction. Following reversal-bake, the wafers are blankexposed (the entire wafer is exposed to UV with no mask) for three times (3X) the original exposure time. During this blank-expose, the regions previously exposed are not affected since the photosensitive material is not present in significant concentration. However, all the other regions that were not exposed during the original exposure go through the typical chemical reaction to delink the photoresist polymer, rendering it soluble in developer. At this point, the wafer is developed for seconds to form the pattern. The wafer is then ashed 3 minutes. The post-bake is not performed, as we are interested in keeping the remaining solvent in the photoresist. This will help in stripping the resist following metallization. The wafers are then etched 5 seconds in 10:1 BOE to remove the native oxide on the Si surface, rinsed and dried. They are then placed in the electron beam evaporator vacuum system and the system pumped to 1 x 10-5 Torr. At this pressure, the evaporation of Aluminum is performed at approximately 4 A/sec, for a thickness of 150 nm. Following deposition, the chamber is vented and the wafers removed, ready for the stripping portion of the liftoff procedure. The standard stripping procedure is performed, with Acetone removing the photoresist. The Aluminum that is deposited on the regions with photoresist is removed along with the resist material, while the regions that were dissolved away remain, forming the desired pattern. This stripping may require slight agitation with a foam tipped applicator to remove some areas of the resist, to allow the Acetone to reach beneath the overlying Aluminum layer, to properly remove the resist material. Following the acetone strip, the wafers are rinsed with methanol, water and then dried. Week 10: Back-side metallization Purpose To deposit contact metal on the wafer back side, and to sinter the Aluminum contacts. The wafers are cleaned per the standard procedure. They are then placed in the electron beam evaporator vacuum system and the deposition procedure is performed similar to week 9, but with a thickness of 200 nm. The wafers are then loaded in to the quartz tube furnace held at 475 o C. The wafers are annealed for 15 minutes, and then removed.