conductor - gate insulator source gate n substrate conductor - gate insulator gate substrate n open switch closed switch however: closed however:

Transcription

1 MOS Transistors Readings: Chapter 1 N-type drain conductor - gate insulator source gate drain source n p n substrate P-type drain conductor - gate insulator source drain gate source p p substrate n 42 Transistor Switches N-type G=0 G=1 = = open switch closed switch however: TRUE = 1 = 4 to 5 Volts FLSE = 0 = 0 to 1 Volts 0 1 good 0 poor 1 P-type G=0 G=1 = = closed switch open switch however: 0 1 poor 0 good 1 43

2 asic Gates Inverter Vdd (source of 1's) GND (source of 0's) Nand Gate Gate: C C C C Nor 44 asic CMOS CMOS is multiple layers of conducting material, separated by insultion. Insulation Contacts/vias are cuts in the insulation to connect layers The interaction of Polysilicon & Diffusion creates transistors Metal 2 Metal 1 Polysilicon Diffusion Substrate 45

3 asic Patterning dd material (e.g., silicon dioxide (SiO2)) pply photoresist Expose through a mask Develop and etch resist Etch material Remove resist silicon wafer photoresist SiO 2 UV light mask 46 dding Material: Growing SiO2 Expose wafer to oxidizing atmosphere at high temperature Wet process: atomosphere with degrees C Dry process: pure 1200 degrees C Oxide grows both ways SiO2 has roughly twice the volume of Si Half above, Half below SiO 2 substrate 47

4 dding Material: Other Techniques Diffusion and Ion Implantation dds dopants to silicon CVD: Chemical Vapor Deposition Silicon, silicon oxide, silicon nitride, etc. Sputtering and thin-film deposition luminum and polysilicon 48 Photoresist UV light sensitive organic material Two types of resist Positive resist: UV light breaks it down Negative resist: UV light hardens it Selectively expose through a mask Masks are glass plates patterned areas stop UV light Develop (harden) desired areas by heating Remove unwanted resist Use weak organic solvent 49

5 Etch Material Etch using selective solvent uffered HF dissolves SiO2 but not Si Photoresist protects areas from etching Plasmas, sputtering, etc. Excited ions blast away material Remove resist with strong organic solvent silicon wafer 50 Mask Making Traditionally a lithographic process Rectangles are 'flashed' onto photographic plate Mechanical alignment limits precision Electron beam techniques are now widely used Write each pixel sequentially oth techniques generate a reticle Typically 10X larger than final size 10X reticle is used to produce final mask Step-and repeat process 10X reticle Mask 51

6 Complete Fabrication (a) field oxide etching (b) p-well diffusion (c) field oxide etching (d) gate oxidation (e) polysilicon definition (g) n-plus diffusion (i) contact cuts (f) p-plus diffusion (h) oxide growth (j) metalization 52 Imperfect Fabrication Process Mask making dust, focusing Growing oxide warping in furnace, uneven reactions Resist over exposed, not hardened enough Etching overetch of resist and/or oxide Multiple layers mask alignment (self-aligning gates helped a lot) Packaging bonding wires to pins of package, handling (macro rules) These problems lead to rules governing layout Rules can be very specific often resulting in 100 page documents 53

7 Minimum Width Rules In wires step coverage on steep oxide cliffs In transistors In contacts/vias safeguard against radically affecting circuit performance must be wide enough for etchant to actually reach layers to be contacted contacts are larger for higher-up layers 54 Minimum Separation Rules In wires far enough apart to prevent short circuits In transistors separate n-type and p-type diffusion regions enough to ensure wells are properly formed In contacts/vias put vias between different layers far enough apart to prevent very irregular terrain from forming it may not be possible to stack vias and ensure that there is no short 55

8 Full-Custom Design Using Full-Custom Design we can get exactly what we want. However: 1.) Complex to design 2.) Takes weeks to fabricate 3.) No economies of scale 4.) How do we automate the mapping? 56 Standard Cells Develop predefined implementations of basic gates with standard form-factor 57

9 Standard Cells Use regular layout Can automate the mapping process, but 1.) Takes weeks to fabricate 2.) No economies of scale S ROUTING S ROUTING S ROUTING S ROUTING S ROUTING S PWR GND PWR GND PWR GND Combine Standard Cell / Full Custom Use full custom for regular structures & critical paths Standard cells handle complex logic & noncritical logic 59

10 Fabrication Process Revisited Speed up fabrication & get economies of scale by prefabricating some layers (a) field oxide etching (b) p-well diffusion (c) field oxide etching (d) gate oxidation (e) polysilicon definition (f) p-plus diffusion (g) n-plus diffusion (i) contact cuts (h) oxide growth (j) metalization 60 Structured SIC - Logic Prefabricate much of the chip 61

11 Structured SIC Routing Customize perhaps only one via level M8 M7 M6 M5 M4 M3 M2 M1 Power & Clock distribution } } Segmented Routing Intra-Logic Tile Routing Corner turns Jumpers for longer routes 62 Discrete Components Prefabricate lots of small, simple parts. Wire them together. D D D D D D 63

12 Programming Technologies Mask-programmed ntifuse N+ diffusion Polysilicon Field Oxide ONO Dielectric EPROM EEPROM access gate n+ source n+ drain floating gate P-Type Silicon SRM Write ~ 64 PLs i1 i2 i3 i4 i5 i6 o1 o2 o3 65

13 Field Programmable Gate rrays (FPGs) Logic cells imbedded in a general routing structure Logic cells usually contain: RM RM RM RM RM RM RM RM RM RM RM RM 5-input function calculator Flip-flops ll features electronically (re)programmable 66 Digitial Logic Implementation lternatives Full Custom Standard Cells Structured SICs PWR GND PWR GND Field-Programmable Gate rrays (FPGs) i1 i2 i3 i4 i5 i6 Programmable Logic Devices o1 Discrete Components 67