Hafnium -based gate dielectrics for high performance logic CMOS applications

Transcription

1 Hafnium -based gate dielectrics for high performance logic CMOS applications T. Kelwing*, M. Trentzsch, A. Naumann, B. Bayha, B. Trui, L. Herrmann, F. Graetsch, R. Carter, R. Stephan, P. Kuecher & W. Hansch * torben.kelwing@cnt.fraunhofer.de Fraunhofer

2 Outline Motivation High-k Integration High-k Material Choice for High Volume Production Deposition Methods Thermal Treatments Summary Fraunhofer 2

3 Historical Oxide Thickness Scaling / Power Limitation [1,2] Shrink slow down Static power exceeds dynamic power despite shrink slow down Gate oxide thickness shrink slow down/stop (due to power limitation) => Finally gate oxide thickness shrink stops No significant gate oxide scaling with Poly/SiON beginning with 90nm node [1] W. Haensch et al. IBM J. RES. & DEV. Vol. 50 No. 4/5, 2006 [2] E.J. Nowak, IBM J. RES. & DEV. Vol. 46 No. 2/3, 2002 Fraunhofer 3

4 Historical Gate Length Scaling L G L G reduction without adequate CET scaling L G scaling stop => Capacitive channel control loss => Increased I D,Off Gate oxide thickness scaling stop enforces L G scaling stop Fraunhofer 4

5 Resulting Integration Challenges Pitch reduction without gate shrink => Less space for contacts Placing contacts is challenging already in older Poly/SiON generations Without CET- and gate-scaling contact formation becomes more and more challenging Fraunhofer 5

6 Solution High-k / Metal Gate Technology High-k / Metal Gate Technology Thicker oxide with same C: Enables CET scaling Solves power limitation issue Enables L G scaling => Simplifies contact formation HK/MG technology required to solve power limitation issue and help contact fabrication Fraunhofer 6

7 Outline Motivation High-k Integration High-k Material Choice for High Volume Production Deposition Methods Thermal Treatments Summary Fraunhofer 7

8 Gate First High-k/Dual-Metal-Gate Integration Gate First High-k/Dual-Metal-Gate process (dep-etch-dep) Crucial for a successful integration Well controlled base oxide (besides the mandatory High-K) Dedicated thin WF capping layers (simplified gate etch process) Metal gate All experiments carried out with respect to Gate First integration Fraunhofer 8

9 HK/MG Gate Leakage Improvement ~8 Å (NMOS) and ~10 Å (PMOS) CET benefit at same leakage HK/MG compared to conventional Poly/SiON technology Fraunhofer 9

10 Performance (early dev) (early dev) +33% +36% Performance benefit (similar V T and C miller ) 45nm Poly/SiON => 45nm HK/MG ~9% 45nm Poly/SiON => 32nm HK/MG ~33% Performance benefit (similar V T and C miller ) 45nm Poly/SiON and 45nm HK/MG similar 45nm Poly/SiON => 32nm HK/MG ~36% Clear performance improvement for HK/MG technology demonstrated Fraunhofer 10

11 Outline Motivation High-k Integration High-k Material Choice for High Volume Production Deposition Methods Thermal Treatments Summary Fraunhofer 11

12 High-k Material Choice Hf- or Zr-based dielectrics are considered to be most promising candidates Reasonable k, E G (ΔE C, ΔE L ) Thermal stability on SiO 2 or SiON Commercial deposition methods available (ALD, MOCVD, PVD) HfO 2 vs. ZrO 2 Problem Crystallization ZrO 2 : higher k-value (tetragonal phase ) ZrO 2 : Increased leakage (smaller E G ) HfZrO 4 with low Zr content might be a good compromise HfSi x O y / HfSi x O y N z Higher thermal stability and T Cryst Decreased k-value Nitridation mitigates k-value degradation Much more expensive (several steps) The final decision for an adequate material has to be made for each technology separately according to its requirements Fraunhofer 12

13 Outline Motivation High-k Integration High-k Material Choice for High Volume Production Deposition Methods Thermal Treatments Summary Fraunhofer 13

14 Deposition Methods suitable for Production PVD Costs Bad interface quality (radiation- or ion-induced plasma damage) [9,10] Bad 3D-conformality (FinFETs, Replacement Gate ) MOCVD Excellent thickness control and conformality Low cost of ownership (high throughputs, long maintenance cycles) Limited 3D-conformality (FinFETs, Replacement Gate) ALD Excellent thickness control and conformality Variability Excellent 3D-conformality (FinFETs, Replacement Gate ) MOCVD and ALD are preferred solutions!!! Question: Are MOCVD and ALD equally good options for Gate First applications? [9] E.P. Gusev et al. IBM J. RES. & DEV. Vol. 50 No. 4/5, 2006 [10] S. Guha et al. MRS Bulletin Vol. 27 Iss. 3, 2002 Fraunhofer 14

15 MOCVD/ALD Comparison Leakage Current / Threshold Voltage V T gate profile related L Gate ~0.5µm Comparable gate leakage current at given CET inv values (NMOS and PMOS) Minor difference between MOCVD and ALD Thickness dependency ~1.2 mv/ Å (MOCVD) and ~1.6 mv/å (ALD) PMOS and SC devices behave similar [11] [11] T. Kelwing et al., Electron Dev. Lett. Vol.31, Issue 10(2010) Fraunhofer 15

16 MOCVD/ALD Comparison Performance HfZrO 4 thickness = 21Å L gate = 35-50nm HfZrO 4 thickness = 21Å L gate = 35-50nm Equivalent NMOS and PMOS transistor performance achieved Fraunhofer 16

17 Outline Motivation High-k Integration High-k Material Choice for High Volume Production Deposition Methods Thermal Treatments Summary Fraunhofer 17

18 PDA/PWFA Description 1. Base oxide formation 2. High-k deposition 3. Post Deposition Annealing (PDA) N WF P WF 1. WF - capping deposition 1 2. WF - capping patterning 3. WF - capping deposition 2 4. Post WF Annealing (PWFA) Metal N WF Metal P WF P WF 1. Metal deposition 2. Post Metal Annealing (PMA) 3. Si gate deposition Fraunhofer 18

19 Gate Leakage Current NH 3 -based anneal N 2 -based anneal Benefit Benefit Benefit CET Benefit NH 3 Treatments NMOS PMOS PDA 0.4Å 0.7Å PWFA 0.2Å 0.5Å (J G const) CET Benefit N 2 Treatments NMOS PMOS PDA 0.5Å 0.3Å (J G const) PWFA degraded degraded Except N 2 PWFA all tested treatments improve J G -CET behavior => Capability to improve TDDB reliability (leakage driven) Fraunhofer 19

20 Performance NH 3 -based anneal N 2 -based anneal 5-6% Readout at comparable CET, V T and C miller No benefit for PDA and PWFA NMOS shows matched performance as well Readout at comparable CET, V T and C miller 5-6% NMOS I D,Sat benefit (best Split, N 2 PDA) 3-4% PMOS ID,Sat benefit (not shown) Reasonable performance benefit demonstrated especially for N 2 (PDA) Fraunhofer 20

21 Summary HK/MG technology is required to solve power limitation issues and to help contact fabrication Gate First HK/Dual- Metal-Gate process is one promising approach for successful HK/MG integration Hf- or Zr- based materials are most promising candidates ALD and MOCVD are equally good options performance wise N 2 and NH 3 thermal treatments are suitable to improve gate dielectric properties Fraunhofer 21

22 Thank You! Fraunhofer 22

23 The work was funded in line with the technology funding for regional development (ERDF) of the European Union and by funds of the Free State of Saxony. P The authors are responsible for the content of the talk Fraunhofer 23