Chapter 4 : ULSI Process Integration (0.18 m CMOS Process)

Transcription

1 Chapter : ULSI Process Integration (0.8 m CMOS Process)

2 Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e) : Donald A. Neamen (00). Semiconductor Devices - Physics and Technology (/e) : S. M. Sze (00) 5. ULSI Technology : C. Y. Chang, S. M. Sze (996)

3 Major Fabrication Steps in MOS Process Flow UV light oxygen Silicon dioxide Silicon substrate Oxidation (Field oxide) photoresist resist Coating Mask exposed photoresist Mask-Wafer Exposed Alignment and Exposure resist oxide resist Develop RF Power RF RF Power Power Ionized CF gas photoresist oxide RF RF Power Power Ionized oxygen gas oxide oxygen gate oxide Dopant gas Silane gas polysilicon RF RF Power Power RF Power Ionized CCl gas oxide poly poly gate gate Oxide resist Strip Oxidation (Gate oxide) Polysilicon Deposition Polysilicon Mask and Scanning ion beam ox S G D Ion ation resist resist resist S G D Active Regions silicon nitride top nitride G S D Nitride Deposition Contact holes S G D Contact Metal contacts drain G S D Metal Deposition and

4 CMOS Manufacturing Steps. Twi s. Shallow Trench Isolation. Gate Structure. LDD s 5. Sidewall Spacer 6. S/D s 7. Contact Formation 8. Local Interconnect 9. Interlayer Dielectric to Via- 0. Metal- Layer. ILD- to Via-. Metal- Layer to Via-. Metal- to Pad. Parameter Testing 8 Via LI metal n + 7 M- Passivation layer ILD-6 M- M- M- 9 Poly gate ILD-5 ILD- ILD- ILD- ILD- p + p + STI n + n p - Epitaxial layer p + Silicon substrate 6 Bonding pad metal p +

5 & Formation Phosphorus implant resist 5 Mask # Oxide 5 ~5 um (Dia = 00 mm, ~ mm thick) Boron implant resist Mask # Oxide 5 Twin well process

6 STI Trench & STI Oxide Fill STI : shallow trench isolation Selective etching opens isolation regions in the epi layer. resist Nitride +Ions Mask # Oxide STI trench Trench fill by chemical vapor Oxide Trench CVD oxide Nitride Liner oxide 6

7 STI Oxide -Nitride Strip & Poly Gate Structure Process Planarization by chemical-mechanical polishing STI oxide after polish Nitride strip(hot phosphoric acid) Liner oxide ARC: antireflective coating Polysilicon Gate oxide resist ARC Poly gate etch Mask # 7

8 n - LDD & p - LDD LDD : lightly doped drain Arsenic n- LDD implant resist mask Mask #5 n- n- LDD tech. are used to reduce the occurrence of current leakage in channel (due to punchthrough effect) BF p- LDD implant n- resist Mask resist mask n- p- Mask #6 p- n- n- p- 8

9 Side Wall Spacer Formation & n + S/D (The dry plasma etcher removes most of the CVD oxide leaving behind the thicker oxide on the sidewalls of the polysilicon gates.) Spacer etchback by anisotropic plasma etcher +Ions Spacer oxide Side wall spacer n- p- p- n- n- p- Sidewall spacers will be used alongside the poly gates to prevent the higher S/D implant from penetrating too close to the channel where S/D pumchthrough could occur. Arsenic n+ S/D implant resist mask Mask #7 n+ n+ n+ 9

10 p + Source/Drain & Contact Formation Boron p+ S/D implant resist Mask resist mask Mask #8 n+ p+ p+ n+ n+ p+ Titanium depostion Tisilicide contact formation (anneal) Titanium etch n+ p+ p+ n+ n+ p+ 0 Chemicals etch away the unreacted Ti, leaving behind tisilicide over the active silicon areas.

11 LI Oxide as a Dielectric for Inlaid LI Metal (Damascene) & LI Oxide Dielectric Formation LI metal LI : local interconnect Doped oxide CVD Mask #9 Nitride CVD Oxide polish etch

12 LI Metal Formation & Via- Formation Ti: double-adhesive tape to hold W to the SiO TiN: a diffusion barrier for the tungsten metal Ti/TiN Tungsten LI tungsten polish ILD : interlayer dielectric Ti ILD- oxide Oxide polish ILD- oxide etch (Via- formation) ILD- Mask #0

13 Plug- Formation Ti/TiN Tungsten Tungsten polish (Plug-) Ti dep. ILD- SEM Micrographs of Polysilicon, Tungsten LI and Tungsten Plugs : Tungsten LI Polysilicon Micrograph courtesy of Integrated Circuit Engineering Mag. 7,000 X Tungsten plug

14 Metal- Interconnect Formation Ti Deposition Al + Cu (%) TiN Metal- etch ILD- Mask # SEM Micrographs of First Metal Layer over First Set of Tungsten Vias : Micrograph courtesy of Integrated Circuit Engineering Mag. 7,000 X TiN metal cap Metal, Al Tungsten

15 Via- Formation ILD- oxide Oxide polish ILD- oxide etch (Via- formation) ILD- gap fill ILD- Mask # 5

16 Plug- Formation Ti/TiN Tungsten polish Tungsten (Plug-) Ti ILD- ILD- 6

17 Metal- Interconnect Formation Metal- to etch ILD- oxide Via-/Plug- formation polish Gap fill ILD- ILD- ILD- 7

18 Full 0.8 mm CMOS Cross Section Passivation layer ILD-6 Bonding pad metal M- ILD-5 ILD- M- ILD- M- LI metal Via M- Poly gate ILD- ILD- n + p + p + STI n + n + p + p - Epitaxial layer 8 p + Silicon substrate

19 SEM Micrograph of Cross-section of AMD Microprocessor Micrograph courtesy of Integrated Circuit Engineering Mag. 8,50 X 9

20 Micromanipulator Prober (Parametric Testing) courtesy of Advanced Micro Devices 0