All Silicon Electrode Photo-Capacitor for Integrated Energy Storage and Conversion

Transcription

1 Supporting Information All Silicon Electrode Photo-Capacitor for Integrated Energy Storage and Conversion Adam P. Cohn 1,, William R. Erwin 3,,, Keith Share 1,2, Landon Oakes 1,2, Andrew S. Westover 1,2, Rachel E. Carter 1, Rizia Bardhan 3, and Cary L. Pint 1,2 * 1 Department of Mechanical Engineering, 2 Interdisciplinary Materials Science Program, and 3 Department of Chemical Engineering, Vanderbilt University, Nashville TN * cary.l.pint@vanderbilt.edu equal contributing authors 1. Material Fabrication Double side polished, boron doped (100) silicon wafers with resistvity Ωcm were etched using an AMMT wafer-scale silicon etching system with an electrolyte of 3:8 v/v hydrofluoric acid and ethanol. For etching, a closed-back wafer holder was used to prevent electrolyte contact with the rear side. Etching was performed at 45 ma/cm 2 for 360 seconds, resulting in an 8 μm deep porous layer, with pores ~25 nm in diameter on average. The porous region was estimated to be ~75% porosity using reflectometry with a specific surface area 1 of ~140 m 2 /cm 3. In order to then etch the opposite side, the silicon wafer was flipped, ensuring that bulk silicon was in contact with the back electrical contact, and the etching procedure was repeated. In general, increasing the etching time increases the depth of the pores and increasing the etching current increases the diameter of the pores. The etching procedure reported is one of many conditions that could be utilized to produce porous silicon materials, and hence we 1

2 anticipate that optimization routes building upon an extensive parameter space for porous silicon fabrication could be utilized to obtain greater area-specific capacitance and hence energy density in the supercapacitor. The few-layered carbon coating was simultaneously grown on both side of the double-sided porous silicon using the following chemical vapor deposition procedure. Double-sided etched silicon was loaded into a quartz tube furnace and heated to 650 o C under atmospheric pressure with a flow of 200 sccm H 2 and 1 slm Ar. Next, 10 sccm of C 2 H 2 was introduced, the temperature was ramped to 750 o C and held for 10 minutes, then the temperature was ramped to 850 o C and held for 10 minutes again. Afterward, the Ar flow was halted and the furnace was cooled to room temperature. Figure S1. (a) High angle annular dark field (HAADF) scanning transmission electron micrograph (STEM) of carbonized porous silicon was captured with energy-dispersive spectroscopy (EDS) maps of (b) silicon and c) carbon. SEM images showing carbonized porous silicon from (c) top-down and (e) profile view. 2

3 Figure S2. Raman spectroscopic characterization of the carbonized porous silicon taken with a 532 nm laser, showing a silicon peak near 520 cm -1 and prominent carbon peaks at ~1340 cm -1 (D peak) and ~1590 (G peak) that indicate defective sp 3 carbon bonding and sp 2 carbon networks respectfully. The less pronounced carbon peaks near ~2650 cm -1 (2D) and 2900 cm -1 (D+D ) arise from two-phonon processes 2. 3

4 Figure S3. Top-down Raman maps consisting of 100 spectra (using 50x objective and 532 nm laser) showing conformal coating and carbon quality for carbonized porous silicon. Map (a) shows the relative intensity of the Si peak to the carbon G peak, indicating minimal change in carbon coverage and map (b) shows the relative intensity of the carbon D peak to the carbon G peak, indicating minimal change in carbon quality. Histograms (c, d) show the same data quantitatively, with each count corresponding to a Raman spectrum. 4

5 Edge of bulk Si Figure S4. (a) Cross-sectional Raman measurements (using 100x objective and 532 nm laser) taken of the carbonized porous silicon are plotted comparing both the relative intensities of the carbon D peak to the carbon G peak and the Si peak to the carbon G peak. (b) Photograph of carbonized porous silicon electrode prior to device assembly. (c) Raman comparison (using 532 nm laser) of the carbon coating on the top and bottom of the double-sided carbonized porous silicon electrode. 2. Device Fabrication The supercapacitor portion of the device was assembled using one piece of double-sided carbon-coated porous silicon (electrode 2) and one piece of single-sided carbon-coated porous silicon (electrode 3). The two electrodes were vacuum infiltrated with a composite of poly(ethylene oxide) (PEO) and 1-ethyl-3-methylimidizolium tetrafluoroborate (EMIBF 4 ) using 5

6 a PEO:EMIBF 4 mass ratio of 1:3 and then the electrodes were sandwiched together forming a solid-state supercapacitor. The dye sensitized solar cells anode were prepared accordingly: FTO glass (MTI) was treated with TiCl 4 (40 mm in Milli-Q water) for 30 minutes at 70 C in order to form a thin TiO 2 sol-gel layer on the FTO surface, followed by a 30 minute, 450 C anneal in air. Next, TiO 2 paste (Dyesol) was doctor bladed onto the FTO glass using Scotch Magic Tape (3M) as a spacer, and subsequently annealed at 450 C for 30 minutes, resulting in a ~10 μm film. Next, a second TiCl 4 treatment was carried out (40 mm in Milli-Q water) for 30 minutes at 70 C, as this step is essential for good electron transport through the system. The electrode was then soaked in N719 dye (Sigma, 0.3 mm in ethanol) overnight, and stored in an N 2 environment until use. Finally, the DSSC anode (electrode 1) was affixed to electrode 2 using a heated surlyn seal (MTI) and then an electrolyte composed of 50 mm I 2, 500 mm LiI, and 500 mm tertbuylpyridine (TBP) in acetonitrile was injected into the encapsulated area between the two electrodes. 6

7 Figure S5. Characterization of the TiO 2 layer. (a) SEM image showing the TiO 2 structure and (b) Raman characterization of the post-annealed TiO 2 taken with a 785 nm laser showing characteristic anatase TiO 2 Raman peaks Testing procedure for integrated photo-capacitor Prior to testing, a mechanical switch was setup to connect/disconnect device electrodes 1 and 3. In addition, a procedure to control the potentiostat was modified to allow for rapid switching from photo-charging mode to Galvanostatic discharge mode using a voltage cutoff trigger. The potentiostat leads were connected to electrodes 2 and 3 and the device was fully discharged before testing began. The mechanical switch was then activated, connecting electrode 1 and 3. An electrical tape mask was fixed to the front of the device (electrode 1) in order to control the area of light exposure. The device was illuminated using AM 1.5 illumination (100 mw/cm 2 ) until a specified cutoff voltage was reached across electrodes 2 and 3. At this point, the solar simulator light was shielded, leaving the device in the dark; the switch was opened in order to disconnect electrodes 1 and 3 to prevent a backflow of current; and the potentiostat began 7

8 Galvanostatically discharging the device. Measurements of the dynamic charging current were made by attaching the leads to electrodes 1 and 3 during illumination (shown in Figure 4B). Figure S6 shows the voltage profile measured when demonstrating maximum device efficiency of 2.1%. Here, the voltage cutoff was lowered to 0.6 V in order to shorten the photocharging time and allow for better average solar conversion efficiency because, as shown in the I-V Curve in Figure 3, the device operates at comparatively low efficiency near the open-circuit voltage. Figure S6. Demonstrating maximum efficiency of 2.1%. Light-charging and dark-discharging curves showing photo-charging to 0.61 V, and subsequent dark Galvanostatic supercapacitor discharging at 0.1 ma/cm 2. 8

9 Figure S7. Demonstrating a longer discharge duration. Light-charging and dark-discharging curves showing photo-charging to 0.64 V, and subsequent dark Galvanostatic supercapacitor discharging at 0.01 ma/cm 2. 9

10 Figure S8. Energy levels and charge transport during charging and discharging. Voltage and current profiles versus time showing three stages of the process: A. Onset of charging, showing the energy levels for maximum photocurrent (J SC ). With no potential built up between electrodes 1 and 2, the iodine redox mediator can continue to reduce the oxidized dye (S + ) to maintain a sufficient population of dye molecules in the ground state (S). The iodine redox mediator is simultaneously reduced at electrode 2, given by the reaction: I e - 3I - B. Saturated charging, as the potential between electrodes 1 and 2 approaches the V OC for the solar cell, the photocurrent decreases to ~0 ma/cm 2. At this point, the over potential needed for the iodine redox process cannot be satisfied and the oxidized dye (S + ) is not sufficiently reduced back to the ground state (S). Meanwhile, the previously photo-generated charges are stored at electrodes 2 and 3 with the formation of an electrostatic double layer in the ionic polymer near the surface of the electrodes. The double layer effectively shields the repulsive electrostatic forces in the charging electrodes, allowing the electrodes to store more charge per volt. The dotted potential line, ψ, illustrates the potential that has built up in the ionic polymer. In the top right of the figure, an illustration shows the possible distribution of the ions. C. Galvanostatic discharging, electrodes 1 and 3 have been disconnected and the device is discharged at a constant current. After a full discharge, the switch connecting electrodes 1 and 3 can be flipped back on and the full process can be repeated again, as show Figure S6 with 10 cycles. 10

11 Figure S9. Light-charging and dark-discharging curves showing 10 cycles with Galvanostatic supercapacitor discharging at 0.5 ma/cm 2. Figure S10. Cycling the supercapacitor component 3000 times at 0.5 ma/cm 2. Inset shows cyclic voltammograms taken before and after cycling using a scan rate of 25 mv/s. 11

12 Figure S11. Demonstrating the stability of the DSSC component over two hours. Figure S12. Demonstrating the ability of the photo-capacitor to hold charge. Voltage profile after charging with no external current flow. After equilibration, virtually no charge is lost over a period of 50 minutes. 12

13 Figure S13. I-V Curve comparison showing the device-to-device variability of the DSSC component for three different integrated devices. Figure S14. Demonstrating the energy and power density of the discharge depending on the discharge current for six different discharge currents. 13

14 REFERENCES 1. Gaur, G.; Koktysh, D. S.; Weiss, S. M. Adv. Funct Mater. 2013, 23, Ferrari, A. C.; Basko, D. M. Nat.Nanotechnol. 2013, 8, Tang, H.; Prasad, K.; Sanjines, R.; Schmid, P.; Levy, F. J. Appl. Phys. 1994, 75,