This Appendix discusses the main IC fabrication processes.

Size: px
Start display at page:

Download "This Appendix discusses the main IC fabrication processes."

Transcription

1 IC Fabrication B B.1 Introduction This Appendix discusses the main IC fabrication processes. B.2 NMOS fabrication NMOS transistors are formed in a p-type substrate. The NMOS fabrication process requires involves nine main steps. 1. DEVELOP SILICON WAFER. Initially a single crystal of silicon of high purity is doped with a p-type material (such as Boron). Wafers are normally circular of between 75 and 150mm in diameter. 2. APPLY THIN LAYER OF O 2. A layer of silicon dioxide (O 2 ) is deposited on the surface of the wafer (approximately 1µm thick). This protects the surface of silicon from damage and also provides an insulating substrate onto which other layers are deposited. Oxide growth 3. APPLY PHOTORESIST. Photoresist is applied to the surface and the wafer is spun to achieve an even distribution. Protoresist 4. APPLY MASK 1 ( THINOX ). The thinox mask is applied and UV light 243

2 shines through the mask to harden the areas of photoresist. The thinox mask defines the areas where transistor channels are formed. UV light 5. ETCH. Areas that have not been exposed are etched away. 6. REMOVE PHOTORESIT. APPLY O 2. The remaining photoresist is removed and a thin layer of O 2 is deposited (approximately 0.1µm). 7. DEPOSIT POLYSILICON. APPLY PHOTORESIST. APPLY MASK 2 (POLYSILICON). ETCH. A thin layer of polysilicon is deposited (1-2µm). Photoresist is again applied and the polysilicon is mask is applied. Again it is etched. 8. PHOTORESIST. APPLY MASK 3 (DIFFUSION). ETCH. DIFFUSE. Photoresist is deposited and the diffusion mask is applied and etched to expose areas where diffusion is to take place. 244 Appendix B

3 9. APPLY O 2. PHOTORESIST. APPLY MASK 4 (CONTACT CUTS). Apply O 2, photoresist and apply mask 4. Wafer is then etched to expose contact cuts. 10. APPLY METAL. APPLY MASK 5 (METAL). ETCH. The whole chip then has metal (aluminium) deposited over its surface to a thickness of typically 1µm. This metal layer is then masked and etched to form the required interconnection pattern. 11.OVERGLASS. An overglass is applied to the wafer to protect the wafer from damage and contamination. Only the bonding pads are unglassed. Notes: 1. When applying diffusion the wafer is heated to a high temperature and a gas containing the desired n-type impurity (such as phosphorus) is passed over the surface. 2. It normally takes a few hours to deposit the O 2 oxide in a wet-oxidation furnace at 1000 o C and is grown on the silicon by heating either pure oxygen or in an atmosphere containing water vapour. 3. Photolithography is the method of patterning the layers of the IC. B.3 CMOS fabrication As discussed in the text there are several approaches to CMOS fabrication, including p-well, n-well, twin-tub and silicon-on-insulator. B.3.1 p-well process The p-well process uses an n-type substrate in which p-type transistors (PMOS) are fabricated. For n-type transistors (NMOS) a tub of p-type is diffused into the n-type substrate. The concentration and depth of the diffusion is important as it defines the threshold voltage of the transistor. A deep well or high well resistivity achieves a low threshold voltage. The main masks used are: 1. DEVELOP SILICON WAFER. APPLY O 2. APPLY PHOTORESIST. CMOS fabrication 245

4 Initially a single crystal of silicon of high purity is doped with an n-type material. O 2 and photoresist are applied to the surface. 2. APPLY MASK 1 (P-WELL MASK). ETCH. DIFFUSE. Areas of p-well are defined and are diffused with p-type material. 3. APPLY PHOTORESIST. APPLY MASK 2 ( THINOX ). ETCH. The thinox mask defines the areas where transistor channels are formed. 4. APPLY THIN LAYER OF O2. DEPOSIT POLYSILICON. APPLY PHOTORESIST. APPLY MASK 2 (POLYSILICON). ETCH. A thin layer of O2 and then a layer of polysilicon (1-2µm). Photoresist is again applied and the polysilicon is mask is applied. The polysilicon is then etched to the required pattern. 5. APPLY PHOTORESIST. APPLY MASK 4 ( THINOX ). ETCH. Photoresist is again applied and the thinox mask is mask is applied. Again it is etched. 246 Appendix B

5 6. APPLY MASK 5 (POSITIVE OF P+ MASK). DIFFUSE WITH P-TYPE. The p+ mask and mask 2 are used to defined the areas in which n-type material is diffused in the substrate. p+ mask (positive) 7. APPLY MASK 6 (NEGATIVE OF P+ MASK). DIFFUSE WITH N-TYPE. A negative of the p+ mask and mask 2 are used to define the areas in which n-type material is diffused in the substrate. p+ mask (negative) 9. APPLY O 2. PHOTORESIST. APPLY MASK 7 (CONTACT CUTS). Apply O 2, photoresist and apply mask 4. Wafer is then etched to expose contact cuts. 10. APPLY METAL. APPLY MASK 8 (METAL). ETCH. The whole chip then has metal (aluminium) deposited over its surface to a thickness of typically 1µm. This metal layer is then masked and etched to form the required interconnection pattern. 11. OVERGLASS. An overglass is applied to the wafer to protect the wafer from damage and contamination. Only the bonding pads are unglassed. CMOS fabrication 247