Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Transcription

1 Microelettronica Planar Technology for Silicon Integrated Circuits Fabrication 26/02/2017 A. Neviani - Microelettronica

2 Introduction Simplified crosssection of an nmosfet and a pmosfet Simplified crosssection of a CMOS process with 4 levels of metal A. Neviani - Microelettronica 2

3 Introduction Cross-section of a real 130nm MOSFET Cross-section of a real CMOS process A. Neviani - Microelettronica 3

4 Silicon planar technology: ingredients interconnections and gates: metal interconnects inter-metal vias MOSFET's gates oxide and other insulators: thick, inter-layer dielectric (ILD) thin, high-quality gate oxide trench isolation between devices substrate: p (or n) type silicon monocrystal doping: insert donor/acceptors in welldefined areas with a given depth create layers with uniform donor/acceptor concentration A. Neviani - Microelettronica 4

5 Photolitography Technique used to define geometrical patterns on a semiconductor substrate Needed to: dig holes/trenches define shapes by selective etching implant/diffuse dopant A. Neviani - Microelettronica 5

6 Photolitography SiO 2 layer Example: patterning of a window in a SiO 2 layer Si substrate photoresist SiO 2 layer Si substrate Step 1: photoresist deposition. Photoresist (PR) is an organic polymer sensitive to UV light. Positive PR: when exposed to light becomes soluble to PR developer Negative PR: when exposed to light becomes insoluble to PR developer A. Neviani - Microelettronica 6

7 Photolitography UV light mask exposed PR SiO 2 layer Step 2: photoresist exposure PR is selectively exposed to UV light using a mask Si substrate exposed PR dissolved by developer SiO 2 layer Si substrate Step 3: photoresist development PR washed in a developer solution Assuming positive PR was used, the portion of PR exposed to UV light in step 2 is dissolved by developer A. Neviani - Microelettronica 7

8 Photolitography SiO 2 layer SiO 2 layer SiO 2 etched by HCL Si substrate Step 4: oxide etching Chemical etching using HCl SiO 2 below PR window reacts with HCl and is removed PR is insensitive to HCl and protects SiO 2 When SiO 2 below PR window is completely removed, reaction stops as Si is insensitive to HCl Step 5: photoresist removal Unexposed PR is removed, leaving the desired patterned oxide Si substrate A. Neviani - Microelettronica 8

9 Silicon crystal growth Starting material: SiO 2 Highly impure metallurgical Si obtained from: Then SiO 2 + 2C Si + 2CO (impure) Si + HCl SiHCl 3, SiCl 4 and impurities A. Neviani - Microelettronica 9

10 Silicon crystal growth Then, high purity poly-crystalline Si is produced from trichlorosilane or Si tetrachloride 1100 C 2SiHCl 3 + 2H 2 2Si + 6HCl A. Neviani - Microelettronica 10

11 Silicon crystal growth Si monocrystal ingot grown by Czochralski method break-up of a polycrystalline Si bar A. Neviani - Microelettronica 11

12 Silicon crystal growth From poly-crystalline silicon to silicon monocrystal ingot A. Neviani - Microelettronica 12

13 Silicon crystal growth Final result: Si monocrystal without defects Ingot of large diameter (up to 12 ) high purity (1 part per billion, i.e cm -3 impurity on cm -3 silicon atoms) A. Neviani - Microelettronica 13

14 Silicon wafers production Ingots are sliced in thin (0.3 1 mm) wafers Wafer surfaces are mechanically and chemically polished A. Neviani - Microelettronica 14

15 Silicon wafers production Si wafer surface after slicing Si wafer surface after polishing A. Neviani - Microelettronica 15

16 Silicon epitaxial growth Used to grow a thin layer of single-crystal silicon over a single-crystal silicon substrate Advantages improved doping control better bipolar devices prevention of latch-up in CMOS circuits Epitaxial growth techniques chemical vapor deposition (CVD) molecular beam epitaxy (MBE) A. Neviani - Microelettronica 16

17 Chemical vapor deposition (CVD) Reactants (gases and dopant) are transported to the substrate regions They are transferred to the substrate surface where they are absorbed The chemical reaction occurs, followed by the growth of the epitaxial layer The produces gases are desorbed The reaction product are transported out from the reactor A. Neviani - Microelettronica 17

18 Molecular beam epitaxy (MBE) Thermal beams of atoms or molecules produced in evaporators condense on a crystalline surface under ultra high vacuum (10-8 Pa) The result is a single crystal structure with thickness control of one atomic layer and precise doping concentration A. Neviani - Microelettronica 18

19 Molecular beam epitaxy (MBE) A. Neviani - Microelettronica 19

20 Film growth and deposition Thermal oxidation gate thin oxide surface thick oxide Dielectric deposition inter-metal insulation Polysilicon deposition gates and local interconnections Metallization interconnections and pads A. Neviani - Microelettronica 20

21 Thermal oxidation of Silicon Used to grow films of SiO 2 on the Si substrate surface Key factor in determining the success of Si technology naturally grown by Si oxidation good quality Si/SiO 2 interface low impurity and defect concentration in SiO 2 Dry oxidation Si (solid) + O 2 (gas) SiO 2 (solid) Wet oxidation (with water vapor much faster!) Si (solid) + 2H 2 O (gas) SiO 2 (solid) + 2H 2 (gas) A. Neviani - Microelettronica 21

22 Thermal oxidation of Silicon Furnace: quartz tube at high temperature: from 850 C to 1100 C The reaction rate follows an Arrhenius law: v A exp (-Ea/kT) Ea = Activation energy [ev] A. Neviani - Microelettronica 22

23 Oxide growth law During the oxidation, part of the silicon reacts and is consumed Si0 2 : molecules/cm 3 Si: atoms/cm 3 Then, the consumed silicon thickness is 0.44 times the thickness of the formed SiO X ox 0.44X ox X ox A. Neviani - Microelettronica 23

24 Oxide growth law Three phases: (1) transfer of the reactants to the SiO 2 (2) diffusion of reactants through formed SiO 2 (3) reaction with the Si F(1) = gas flux at the surface F(2) = diffusion through SiO 2 F(3) = reaction rate at the SiO 2 /Si C 0 = oxidant species concentration at the surface C i = oxidant species concentration at the SiO 2 /Si interface A. Neviani - Microelettronica 24

25 Oxide growth law x ox x ox C i Basic model for the thermal oxidation of silicon 1. Transfer of the reactants to the SiO 2 F * h C 1 C 0 F(1) = gas flux at the surface h = mass transfer coefficient in gaseous phase C * = oxidant species concentration at equilibrium in the oxide C 0 = oxidant species concentration at the surface A. Neviani - Microelettronica 25

26 Oxide growth law x ox x ox C i Basic model for the thermal oxidation of silicon 2. Diffusion through the formed SiO 2 C C F2 D 0 i xox D = diffusivity x ox = oxide thickness (C 0 - C i )/x ox = concentration gradient in the SiO 2 A. Neviani - Microelettronica 26

27 Oxide growth law 3. Oxidation reaction rate at the SiO 2 /Si interface: x ox F 3 k s C i C i k s = surface reaction rate x ox Basic model for the thermal oxidation of silicon A. Neviani - Microelettronica 27

28 Oxide growth law At steady state: F(1)=F(2)=F(3)=F thus starting from A. Neviani - Microelettronica 28 i s ox i * C k x C C D C C h 0 0 s ox s i i s ox i k D x C D F k F C F C k x C C D 0 0

29 Oxide growth law Then, using Solving for F A. Neviani - Microelettronica 29 s ox * * * k D x h F C D F C h F C F C C h 0 0 D k x h k C k F s ox s * s 1

30 Oxide growth law Growth rate R (thickness per unit time) given by ratio of flux F over number of oxidizing molecules required to form a unit volume of SiO 2 : molecules/cm 3 of SiO 2 N ox = cm -3 of O 2 molecules required for dry oxidation OR N ox = cm -3 of H 2 O molecules required for wet oxidation Then R dx dt ox F N ox N ox k 1 k s s C h * x ox k s D A. Neviani - Microelettronica 30

31 Oxide growth law The differential equation can be solved for x ox (t): D 1 k s + 1 h + x ox dx ox = D C N ox x ox 2 + A x ox = B t ox + τ dt ox where A = 2 D 1 k s + 1 h τ = x ox 2 B, B = 2 D C N ox + x ox B A time shift due to initial oxide thickness A. Neviani - Microelettronica 31

32 Oxide growth law x ox t A t A 4 B Short times: growth limited by surface reaction speed B x ox t t A Long times: growth limited by diffusion through SiO 2 x ox t B t B t A. Neviani - Microelettronica 32

33 Oxide growth law B A B D 0 exp E A kt choose appropriate value of D 0 from the table below A. Neviani - Microelettronica 33

34 Oxide growth law linear rate constant B/A parabolic rate constant B A. Neviani - Microelettronica 34

35 Oxide growth law A. Neviani - Microelettronica 35

36 Thin (gate) and thick oxide Micrograph of a cross-section of an active region bounded by LOCOS gate thin oxide p-si substrate thick oxide to isolate MOSFET's A. Neviani - Microelettronica 36

37 Trench isolation Used in modern CMOS technologies (L 250 nm) instead of LOCOS Trenches etched between devices and filled with dielectric material dielectric deposition technique required trench isolation A. Neviani - Microelettronica 37

38 Inter-layer dielectric (ILD) metal7 metal6 inter-metal dielectric metal5 metal4 metal3 metal2 metal1 MOSFET region via connecting metal n to metal n-1 A. Neviani - Microelettronica 38

39 Inter-layer dielectric (ILD) Materials used for ILD SiO 2 ( ox =3.9, used in CMOS processes 250 nm) low-k materials ( lk 2, used to reduce interconnect parasitic capacitance in CMOS processes 180 nm) A. Neviani - Microelettronica 39

40 Inter-layer dielectric (ILD) ILD realization techniques Chemical vapor deposition (CVD) Quality of deposited SiO 2 worse than that of thermally grown SiO 2 used as ILD, doping mask or to increase thickness of thermal oxide A. Neviani - Microelettronica 40

41 Polysilicon deposition Polycrystalline Silicon (polysislicon) used for MOSFET's gates in technologies 1m L 65 nm local interconnections integrated capacitor plates Realized by deposition thermal decomposition of Silane (SiH 4 ) in a low pressure reactor at C SiH 4 Si + 2H 2 A. Neviani - Microelettronica 41

42 Metallization Aluminum metallization for interconnects used until late 90's blanket deposition, then selectively etched to form desired interconnection patterns problems: electromigration, spiking, resistivity Copper (double) damascene technology lower resistivity than Al (1.72 vs 2.73 cm) better resistance to electromigration problems: difficult to pattern using standard etching techniques solution: damascene process A. Neviani - Microelettronica 42

43 Damascene process metal deposition and PR pattern definition metal etching according to PR pattern dielectric deposition etching of excess dielectric dielectric deposition and PR pattern definition etching of trenches for metal lines trenches filled by metal deposition excess metal removed by planarization deposition of dielectric upper layer A. Neviani - Microelettronica 43

44 Damascene process in detail A. Neviani - Microelettronica 44

45 Doping Doping is the process by means of which selected impurities are inserted in a semiconductor substrate Impurities can be of acceptor or donor type and must be in a substitutional position to be active Main dopants for Silicon: Element Group Type Carriers B III P Holes P V N Electrons As V N Electrons Main Technologies: Predeposition + Diffusion Ionic implantation + Recristallization + diffusion A. Neviani - Microelettronica 45

46 Doping by diffusion Predeposition of a fixed amount of dopant in a thin surface layer Diffusion (drive-in) of dopant into the substrate depth of diffusion controlled by drive-in temperature and time SiO 2 predeposition SiO 2 dopant after drive-in p-si substrate A. Neviani - Microelettronica 46

47 Doping by diffusion Ln(C) Predeposition erfc Diffusion t 1 Diffusion t 2 >t 1 Gaussian x A. Neviani - Microelettronica 47

48 Doping by diffusion Predeposition with constant dopant concentration C S at the surface x Dt N x,t CSerfc N' Q 2CS 4Dt pre-doping profile at time t amount of dopant inserted into substrate at time t Drive-in of a fixed amount N' of dopant N x,t Q Dt exp doping profile at time t 2 x 4Dt N 0,t Q Dt surface doping level at time t A. Neviani - Microelettronica 48

49 Doping by ion implantation Dopant ions shot by an ion gun at KeV Ions penetrate into substrate and lose kinetic energy to lattice atoms Patterned oxide acts as mask so that dopant is implanted in selected substrate regions P-Si A. Neviani - Microelettronica 49

50 Doping by ion implantation Ions that enter into the substrate are subject to random inelastic interactions with lattice atoms resulting doping profile shows a Gaussian shape concentration ln(n) P-Si x Gaussian A. Neviani - Microelettronica 50

51 Doping by ion implantation A. Neviani - Microelettronica 51

52 Doping by ion implantation High-energy ions cause severe crystal damage A re-adjustment of the crystal is required through a thermal annealing step Thermal annealing causes a dopant redistribution (due to a diffusion mechanisms) and this is an unwanted effect RTA (rapid thermal annealing): high temperatures (1000 C) for short time (10 sec) limits dopant redistribution A. Neviani - Microelettronica 52

53 Doping by ion implantation Doping profile after implant C(x) C exp x R 2 p 2 2Rp N C p = 2π R p N (or Q) = implanted dose C p = concentration peak p L 2 R p Gaussian width A. Neviani - Microelettronica 53

54 Doping by ion implantation Two parameters R p : projected range R p : standard deviation both depend on ion energy, ion type, substrate material See MK book for implantation data: fig (Boron) fig (Phosphorus) fig (Arsenic) A. Neviani - Microelettronica 54

55 Doping by ion implantation Annealing increases Gaussian width due to diffusion of dopant: N x Q exp L' x L' R p 2 L' 2R 2 p 4Dt A. Neviani - Microelettronica 55

56 Doping by ion implantation before annealing after annealing A. Neviani - Microelettronica 56