Chang Gung University, Tao-Yuan, 333, Taiwan. Industrial Technology Research Institute, Hsinchu 310, Taiwan. Fax:

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1 / The Electrochemical Society Impact of High-κ TaO x Thickness on the Switching Mechanism of Resistive Memory Device Using IrO x /TaO x /WO x /W Structure A. Prakash a, S. Maikap a,*, W. S. Chen b, H. Y. Lee b, F. T. Chen b, M.-J. Kao b, and M.-J. Tsai b a Thin Film Nano Tech. Lab., Department of Electronic Engineering, Chang Gung University, Tao-Yuan, 333, Taiwan b Electronic and Opto-Electronic Research Laboratories, Industrial Technology Research Institute, Hsinchu 310, Taiwan * Corresponding author: sidhu@mail.cgu.edu.tw, Tel: ext Fax: The impact of switching layer thickness on the resistive memory performance and uniformity has been investigated in a simple stack of IrO x /TaO x /W fabricated. The formation of amorphous TaO x and nanocrystalline WO x layers are confirmed from HRTEM image. Bipolar resistive switching memory characteristics with small set/reset and large memory window are observed in all devices after electroforming. The observed TaO x thickness independence of set/reset and low resistance state (LRS) is attributed to the formation of localized nano-filament in TaO x layer. Cumulative probability plot shows tight distribution of LRS. Good data retention with a large resistance ratio of >10 3 at 85 o C is obtained. Introduction As a promising alternative candidate for the next generation non-volatile memory technology, resistive random access memory (RRAM) devices in a simple metalinsulator-metal (M-I-M) structure are being investigated (1-2). In such devices, data bits can be stored as resistance in contrast to charge as in flash devices. The primary advantages of RRAM devices are their scalability down to nanometer scale, good compatibility with the existing complementary metal oxide semiconductor (CMOS) process. The fabrication process becomes even simpler if transition metal oxides (3-13) are used as switching material. Tantalum oxide (TaO x ) is one of the materials getting extensive attention due to its distinguished resistive memory performance especially in terms of endurance characteristics (12-13). The platinum (Pt) as an electrode material in Pt/TaO x /Pt structure is reported due to its high work function and inertness. Iridium (Ir) or iridium-oxide (IrO x ) which is also inert and has a high work function (Ф m > 5 ev) can be chosen as an electrode material (14). Furthermore, IrO x metal electrode in an IrO x /TaO x /W structure can be deposited easily by a sputtering system. In this study, the influence of TaO x thickness on the resistive switching memory performance is investigated using a simple memory stack of IrO x /TaO x /W. Typical highresolution transmission electron microscopy (HRTEM) image revealed the formation of WO x layer along with TaO x layer. Bipolar resistive switching behavior is observed with small set/reset voltage and large resistance ratio irrespective of the TaO x thickness after 379

2 forming. The observed independency of set/reset voltage and low resistance state (LRS) on the thickness of TaO x layer confirms the presence of localized conduction paths in the switching layer. The memory device shows good data retention characteristics at 85 o C. Experiment Details The resistive switching memory devices with 8, 10 and 12 nm tantalum oxide (TaO x ) as a switching material in IrO x /TaO x /W metal-insulator-metal (MIM) structure have been fabricated at room temperature. The tungsten (W) metal layer of ~100 nm-thick as a bottom electrode (BE) was deposited by an rf sputtering on 8 p-type SiO 2, 200 nm/si substrate. Then, a low temperature silicon dioxide (SiO 2 ) layer of approximately 150 nm was deposited and different sizes of via holes ranging from 0.4 to 8µm. The BE contact holes were defined by lithography and etching methods. Subsequently, another lithography step to pattern the device for lift-off was performed. High-κ tantalum oxide (TaO x ) layer with different thicknesses of approximately 8, 10 and 12 nm as a switching layer was deposited by an electron-gun evaporation system keeping the constant deposition rate of 1 nm/min in high vacuum of 4x10-6 Torr. Pure (99.99%) tantalum pentoxide (Ta 2 O 5 ) granulates were used for the evaporation and the substrate was kept at ambient temperature. In order to deposit high work function iridium oxide (IrO x ) as a top electrode (TE), IrO x layer with a thickness of approximately 100 nm was deposited by reactive sputtering using Ir target (>99.999%) with 50% Ar and 50% O 2 gas mixture. The pressure of gas mixture was maintained at 20 mtorr and rf power used for deposition was 50 W. Finally, lift-off process was done to get the resistive switching memory devices. To know the film thickness and interface among deposited stack layers, high resolution transmission electron spectroscopy (HRTEM) images were acquired using FEI Tecnai G2 F-20 field emission system with an operating voltage of 200 kv. The memory device for TEM observation was prepared using an FEI Helios-400s system with an operating voltage of 5kV and Ga + ion source was used to thin down the device. Electrical characterizations were performed using HP 4156C precision semiconductor parameter analyzer. All voltages were applied on the TE and the BE was electrically grounded during all measurements. IrO x TaO x ~9 nm WO x ~5 nm W Figure 1. Cross-sectional HRTEM image of fabricated resistive switching memory device in an IrO x /TaO x /W structure 380

3 Results and Discussion Figure 1 presents the cross-sectional HRTEM image of resistive switching memory device in which the deposited stack layers and their interfaces are clearly visible. The thicknesses of TaO x and self formed tungsten oxide (WO x ) layers are approximately 9 and 5 nm, respectively. The TaO x layer is amorphous while polycrystalline grains can be spotted in WO x layer (not shown here) confirming the nano-crystalline nature of WO x layer. Figure 2 shows the typical current-voltage (I-V) curves of pristine memory devices with TaO x thicknesses of 8 and 12 nm during electro-formation. In the electroforming process, a high voltage or current is applied across the memory device which produces significant and irreversible change in the electrical resistance by introducing the conducting paths or filaments in the insulator material. After the forming process, the memory device can exhibit reversible and non-volatile change in its resistance. In figure 2, when the negative sweep voltage of -10 V was applied on the TE, the devices with TaO x thicknesses of 8 and 12 nm were formed at about -6.3 and -8.6 V, respectively. At the forming voltage (V form ), a sudden increase in the current is observed. The current compliance was 20 µ. Current (A) V form = V V form = V 8 nm, TaO x 12 nm, TaO x Voltage (V) Figure 2. Current-voltage curves of pristine memory devices with TaO x thicknesses of 8 and 12 nm during electroforming process. Moreover, significantly higher forming voltage (-8.6 V) and lower leakage current (1.3x10-12 A at -1.5 V) for 12 nm TaO x device as compared to 8 nm TaO x device with V form of -6.3 V and leakage current of 5.5x10-11 A are observed. In the thicker film, the higher voltage is needed to get the same electric field as compared to thinner film and therefore the V form of 12 nm TaO x device is higher than that of 8 nm device. After forming, the devices exhibit reversible resistive switching behavior irrespective of the TaO x thickness. Figure 3 shows the typical I-V hysteresis curve of memory device in bipolar mode switching with TaO x thickness of 8 nm. The arrows 1 to 4 indicate the path followed by current as a result of applied dc sweep voltage. Typical set and reset voltages 381

4 are -2.0 and +1.2 V, respectively, which are much smaller than the forming voltage (-6.3 V). It is likely that before forming, the applied voltage drops across the entire thickness of switching layer while after formation voltage drop may occur across smaller effective thickness of insulator layer as some part of the conducting nano-filaments, formed during forming process, might remain in the insulator layer after the reset process thereby reducing the effective thickness. Moreover, the comparison of resistance of memory device before and after forming process reveals that the resistance of HRS (2 MΏ) is significantly smaller than initial resistance (IRS) of the pristine device (120 GΏ) indicating the part of the filaments remains after the reset process. It is also observed that the set/reset voltage and LRS is independent of TaO x thickness (Fig. 4) which confirms the formation of localized conducting channels in the TaO x layer. The set voltage is smaller than the reset voltage but reset current (600 μa) is larger than the set or compliance current of 500 μa, which indicates the reset process might not only be driven by oxidation process but also assisted by joule heating at higher voltage. Current (A) V set = -2 V 3 V reset = +1.2 V Voltage (V) Figure 3. Current-voltage (I-V) hysteresis curve of resistive memory device in IrO x /TaO x /WO x /W structure. The large resistance ratio of >10 3 is achieved. Figure 4 shows the forming voltage is increased with TaO x thickness while both set and reset voltages are independent of TaO x thickness, which is a strong evidence of localized conduction in the memory device. Figure 5 shows cumulative probability distribution of LRS and HRS of memory device with 8, 10 and 12 nm-thick TaO x layer. The LRS is independent of TaO x thickness with a tight distribution while HRS increases with decreasing TaO x thickness with the largest average value of approximately 2x10 6 Ω in case of 8 nm-thick TaO x. Moreover, the higher dispersion in HRS as compared to LRS in all the thicknesses is observed, which is not clear at this stage. The memory window is more than

5 Voltage (V) Reset Set Formation TaO x thickness (nm) Figure 4. Dependence of forming, set and reset voltages on the thickness of TaO x layer. Cumulative probability (%) 10 2 TaO x,12nm 10 1 TaO x,8nm LRS -0.2V HRS TaO x,10nm Resistance (Ω) Figure 5. Cumulative probability plot of LRS and HRS of fabricated resistive memory stack in IrO x /TaO x /WO x /W structure with TaO x thicknesses of 8, 10 and 12 nm. Figure 6 shows the typical high temperature data retention characteristics of resistive memory device with TaO x thickness of 8 nm. Excellent data retention of more than 3 hours with stable HRS and LRS is observed. The resistance ratio of >10 3 at a read voltage of -0.2 V is observed. 383

6 Resistance (Ω) HRS LRS Read@ -0.2 V 85 o C Retention time (s) Figure 6. Typical high temperature data retention characteristics of fabricated resistive memory device with TaO x thickness of 8 nm. Conclusions The effect of TaO x switching layer thickness on the resistive switching memory characteristics has been investigated. The memory stack in a simple structure of IrO x /TaO x /W with TaO x thicknesses of 8, 10 and 12 nm shows bipolar switching. The memory device has small set/reset voltage of -2/1.2 V and high HRS/LRS ratio of >10 3. The HRTEM image confirms the formation of amorphous TaO x and nano-crystalline WO x layers. The independence of set/reset and LRS on the TaO x thickness confirms the presence of localized nano-filaments in the TaO x switching material. Non-volatile behavior of both LRS and HRS with large resistance ratio of >10 3 are observed during the data retention at 85 o C. It is expected that the observations made in this study will be helpful in further improving the resistive switching memory device applications. Acknowledgment The authors are grateful to the National Science Council (NSC), Taiwan to support this work under the contract number: NSC E MY3. References 1. R. Waser and M. Aono, Nature Mater., 6, 833 (2007). 2. C.-Y. Lin, C.-Y. Wu, C.-Y. Wu, C. Hu, T.-Y. Tseng, J. Electrochem. Soc., 154, G189 (2007). 3. A. Sawa: Mater. Today, 11 no.6, 28 (2008). 4. H. Y. Lee, Y. S. Chen, P. S. Chen, P. Y. Gu, Y. Y. Hsu, S. M. Wang, W. H. Liu, C. H. Tsai, S. S. Sheu, P. C. Chiang, W. P. Lin, C. H. Lin, W. S. Chen, F. T. Chen, C. H. Lien, M.-J. Tsai, IEDM Tech. Dig., 2010, p J. Y. Son, D. Y. Kim, H. Kim, W. J. Maeng, Y. S. Shin, Y. H. Shin, Electrochem. Solid State Lett., 14, H311 (2011). 384

7 6. S. Jung, J. Kong, S. Song, K. Lee, T. Lee, H. Hwang, S. Jeon, J. Electrochem. Soc., 157, H1042 (2010). 7. W. C. Chien, Y. C. Chen, E. K. Lai, Y. D. Yao, P. Lin, S. F. Horng, J. Gong, T. H. Chou, H. M. Lin, M. N. Chang, Y. H. Shih, K. Y. Hsieh, R. Liu, C.-Y. Lu, IEEE Electron Device Lett., 31, 126 (2010). 8. W. Banerjee, S. Maikap, S. Z. Rahaman, A. Prakash, T.-C. Tien, W.-C. Li, J.-R. Yang, J. Electrochem. Soc., 159 (2), H177 (2012). 9. A. Prakash, S. Maikap, C. S. Lai, H. Y. Lee, W. S. Chen, F. T. Chen, M.-J. Kao, M.-J. Tsai, SSDM 2011, p W. Banerjee, S. Z. Rahaman, A. Prakash, S. Maikap, Jpn. J. Appl. Phys., 50, 10PH01 (2011). 11. S. Yu, B. Gao, H. Dai, B. Sun, L. Liu, X. Liu, R. Han, J. Kang, B. Yu, Electrochem. Solid-State Lett., 13, H36 (2010). 12. Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii, K.Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, T. Takagi, R. Yasuhara, K.Horiba, H. Kumigashira, M. Oshima, IEDM Tech. Dig., 2008, p J. J. Yang, M-X. Zhang, J. P. Strachan, F. Miao, M. D. Pickett, R. D. Kelley, G. M. Ribeiro and R. S. Williams, Appl. Phys. Lett., 92, (2010). 14. W. Banerjee, S. Maikap, T.-C. Tien, W.-C. Li, J.-R. Yang, J. Appl. Phys., 110, (2011). 385