Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.
|
|
- Christopher Logan
- 6 years ago
- Views:
Transcription
1 Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed regions of silicon.
2 Figure 2.2 (p. 59) Evolution of IC technology. (a) First commercial silicon planar transistor (1959). (b) Diode-transistor logic (DTL) circuit (1964). (c) 256-bit bipolar random access memory (RAM) circuit (1970). (d) VLSI central-processor computer chip containing 450,000 transistors (1981). The different functions carried out by the IC are labeled on the figure. [(a), (b), and (c) courtesy of B.E. Deal Fairchild Semiconductor. (d) courtesy of Hewlett-Packard Co.]
3 Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.]
4 Figure 2.2 (cont., p. 60) (f) Minimum feature size versus year of first commercial production.
5 Figure 2.2 (cont., p. 61) (g) Another embodiment of Moore s law shows that the number of transistors per chip has doubled every months for approximately 30 years.
6 Figure 2.2 (cont., p. 61) (h) Along with decreasing feature size, the number of electrons in each device decreases. [(f)-(h) adapted from Mark Bohr, Intel; Howard Huff, Sematech; Joel Birnbaum, Hewlett-Packard; Motorola.]
7 Figure 2.3 (p. 63) Formation of a single-crystal semiconductor ingot by the Czochralski process: (a) initiation of the crystal by a seed held at the melt surface, (b) withdrawal of the seed pulls a single crystal.
8 Figure 2.4 (p. 65) The float-zone process. A molten zone passes through a polycrystalline-silicon rod, and a single crystal grows from a seed at the bottom end.
9 Figure 2.5 (p. 67) An insulating layer of silicon dioxide is grown on silicon wafers by exposing them to oxidizing gases in a high-temperature furnace.
10 Figure 2.6 (p. 67) Three fluxes that characterize the oxidation rate: F(1) the flow from the gas stream to the surface, F(2) the diffusion of oxidizing species through the already formed oxide, and F(3) the reaction at the Si-SiO 2 interface. The concentration of the oxidizing species varies in the film from C o near the gas interface to C i near the silicon interface.
11 Figure 2.10 (p. 73) The intrinsic carrier density n i in silicon between 300 and 1200 C [10].
12 Figures 2.11a and 2.11b (p. 75) (a) The areas from which the oxide is to be etched are defined by exposing a lightsensitive resist through a photographic negative (mask). (b) The hardened resist protects the oxide in the masked areas from chemical removal.
13 Figure 2.11c (p. 75) (c) In a stepper-type lithography system, exposure light passes through features on a mask. The image of each feature is reduced and focused on one die on the wafer, and all features on the die are exposed simultaneously. The wafer is then moved (stepped) to the next die position where the exposure process is repeated.
14 Figure 2.12 (p. 76) (a) The illumination intensity varies gradually near the edge of a fine feature because of diffraction. (b) The intensity between two closely spaced features does not reach zero. Shifting the phase of the electric field by 180 by locally changing the path length through the mask (c) allows the intensity to become zero between the features (d).
15 Figure 2.13a (p. 77) (a) Cross-sectional transmission electron micrograph of a polysilicon gate approximately 180 nm across, the gate oxide under the polysilicon, and the surrounding shallow junctions in the silicon substrate (Courtesy of Accurel Systems International Corp.)
16 Figure 2.13b (p. 77) (b) Anisotropically etched lines 500 nm wide spaced 1.5 μm apart. Resist covers the double-layer structure consisting of 180 nm TaSi 2 over 260 nm of polycrystalline silicon. Note the uniformity of the vertical surface through the various layers. (Courtesy of G. Dorda, Siemens Corporation).
17 Figure 2.14 (p. 79) (a) Isotropic wet etching or dry etching that is dominated by chemical reactions cause significant undercut of the masking layer. (b) Anisotropic, ion-assisted, dry etching creates a near-vertical profile, retaining the dimensions of the masking layer.
18 Figure 2.15 (p. 80) In ion implantation, a beam of high-energy ions strikes selected regions of the semiconductor surface, penetrating into these exposed regions.
19 Figure 2.18 (p. 84) The increase in dopant concentration in a region dx is related to the net flux of atoms into the region: F(x) F(x + dx).
20 Figure 2.20 (p. 86) Temperature dependence of the diffusities (at low concentrations) of commonly used dopant impurities in silicon [12].
21 Figure 2.22 (p. 88) Temperature dependence of the solid solubilities of several elements in silicon [13].
22 Figure 2.23 (p. 92) (a) Scanning electron micrograph showing cross section through a bipolar transistor, (b) sketch identifying the regions shown. The boron-doped base region has been pushed ahead (emitter push) by the concentration-dependent diffusion effects associated with heavy phosphorus doping in the emitter [15].
23 Figure 2.24 (p. 93) Section of a silicon wafer showing deeper diffused n-type region (dark area) under oxidized silicon surface (bottom) than underneath a surface protected from oxidation (top) [16].
24 Figure 2.25 (p. 96) (a) Lightly doped epitaxial layer grown on heavily doped silicon substrate. (b) Singlewafer, epitaxial deposition system showing silicon wafer on support plate that is heated by infrared lamps located outside the quartz deposition chamber.
25 Figure 2.26 (p. 98) LOCal Oxidation of Silicon (LOCOS). (a) Defined pattern consisting of stress-relief oxide and Si 3 N 4 covering the area over which further oxidation is not desired, (b) thick oxide layer grown over the bare silicon region, (c) stress-relief oxide and Si 3 N 4 removed by etching to permit device fabrication, (d) scanning electron micrograph (5000 X) showing LOCOSprocessed wafer at step (b).
26 Figure 2.27 (p. 99) Trench isolation is used to form very narrow isolation regions between adjacent devices. After the trench pattern is etched in a masking material (a), the trench is etched directionally using a reactive ion etch process (b). A thin, high-quality oxide is formed (c), and the trench is filled with polysilicon or with oxide [shown for oxide in (d)]. The excess material is removed by chemical-mechanical polishing (e).
27 Figure 2.28 (p. 100) (a) Section along horizontal, open-flow reactor showing gas flow parallel to the wafer surface and indicating the location of the boundary layer in which the gas flow is nearly perpendicular to the wafer surface, (b) representation of gas velocity distribution across the reaction chamber.
28 Figure 2.31 (p. 102) (a) Gases in a high-capacity reactor flow through the annular space between the wafers and reactor wall and then diffuse between the closely spaced wafers. (b) The basic elements of a LPCVD reactor.
29 Figure 2.32a (p. 103) (a) Schematic cross section of a remote plasma-enhanced CVD reactor, in which the plasma generation, the chemical reaction, and the ion bombardment are partially decoupled.
30 Figure 2.32b (p. 103) (b) Schematic cross section of an electron cyclotron resonance, highdensity plasma reactor.
31 Figure 2.33 (p. 104) A thin layer of aluminum can be used to connect various doped regions of a semiconductor device.
32 Figure 2.34 (p. 105) (a) In the salicide process Ti is deposited over the entire wafer and annealed to form TiSi 2 over the exposed silicon. The unreacted Ti over the oxide is then removed by wet chemical etching. (b) Cross-sectional transmission electron micrograph of silicide formed by the salicide process over the gate, source, and drain regions of an MOS transistor. (Courtesy of Accurel Systems International Corp.)
33 Figure 2.35 (p. 107) Cross-sectional transmission electron micrograph of three levels of a multilevel interconnection system. Three levels of aluminum metallization and associated barrier layers are visible, along with the tungsten-filled (black) vias between metal layers. Polysilicon lines are visible just above the substrate. (Courtesy of Rudolph Technologies, Inc.)
34 Figure 2.36 (p. 107) Cross-sectional transmission electron micrograph showing a more detailed view of tungsten plugs connecting the underlying silicide layer and the overlying aluminum first metallization layer. (Courtesy of Accurel Systems International Corp.)
35 Figure 2.37 (p. 111) Electromigration mechanism in a conducting stripe. Directions of electron flux F e, electrostatic force qξ and resultant atomic flux F A (upper left). Scanning electron micrograph showing void formation to the left of the break and accumulation of material in the form of hillocks to the right of the break (lower figure). The steps leading to electromigration failure are indicated at the upper right [18].
36 Figure 2.38 (p. 112) The IC chip is mounted in a package, and wires are connected to the external leads.
37 Figure 2.39 (p. 115) Electrical device performance can be improved by combining two semiconductors with different bandgaps. However, lattice mismatch and the associated strain limit the useful heteroepitaxial combinations of materials.
38 Figure 2.45 (p. 129) (a) An IC resistor defined by diffusing acceptors into selected regions of an n-type wafer. The p + regions are highly doped to assure good contact between the metal electrodes and the p-type resistor region. (b) The dimensions of a thin region in the resistor having conductance dg given by Equation
EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO
More informationEE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time IC Fabrication Technology Crystal Preparation
More informationChapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
More informationEE 330 Lecture 9. IC Fabrication Technology Part 2
EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this
More informationCzochralski Crystal Growth
Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling
More informationEE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects
EE 330 Lecture 8 IC Fabrication Technology Part II - Oxidation - Epitaxy - Polysilicon - Interconnects Review from Last Time MOS Transistor Bulk Source Gate Drain p-channel MOSFET Lightly-doped n-type
More informationFabrication and Layout
ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide
More informationChapter 3 CMOS processing technology
Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),
More informationEE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
More informationCHAPTER - 4 CMOS PROCESSING TECHNOLOGY
CHAPTER - 4 CMOS PROCESSING TECHNOLOGY Samir kamal Spring 2018 4.1 CHAPTER OBJECTIVES 1. Introduce the CMOS designer to the technology that is responsible for the semiconductor devices that might be designed
More informationMicroelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica
Microelettronica Planar Technology for Silicon Integrated Circuits Fabrication 26/02/2017 A. Neviani - Microelettronica Introduction Simplified crosssection of an nmosfet and a pmosfet Simplified crosssection
More informationHOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:
HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
More informationFabrication Technology
Fabrication Technology By B.G.Balagangadhar Department of Electronics and Communication Ghousia College of Engineering, Ramanagaram 1 OUTLINE Introduction Why Silicon The purity of Silicon Czochralski
More informationEE 434 Lecture 9. IC Fabrication Technology
EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and
More informationA discussion of crystal growth, lithography, etching, doping, and device structures is presented in
Chapter 5 PROCESSING OF DEVICES A discussion of crystal growth, lithography, etching, doping, and device structures is presented in the following overview gures. SEMICONDUCTOR DEVICE PROCESSING: AN OVERVIEW
More informationFabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB
Fabrication Process Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation 1 Fabrication- CMOS Process Starting Material Preparation 1. Produce Metallurgical Grade Silicon
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationVLSI Digital Systems Design
VLSI Digital Systems Design CMOS Processing cmpe222_03process_ppt.ppt 1 Si Purification Chemical purification of Si Zone refined Induction furnace Si ingot melted in localized zone Molten zone moved from
More informationIntroduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design
Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each
More informationPROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS
Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative
More informationLecture 22: Integrated circuit fabrication
Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................
More informationVLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical
More informationELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing
ELEC 3908, Physical Electronics, Lecture 4 Basic Integrated Circuit Processing Lecture Outline Details of the physical structure of devices will be very important in developing models for electrical behavior
More informationCMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook
CMOS Fabrication Dr. Bassam Jamil Adopted from slides of the textbook CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different
More informationLecture 2: CMOS Fabrication Mark McDermott Electrical and Computer Engineering The University of Texas at Austin
Lecture 2: CMOS Fabrication Mark McDermott Electrical and Computer Engineering The University of Texas at Austin Agenda Last module: Introduction to the course How a transistor works CMOS transistors This
More informationLecture 1A: Manufacturing& Layout
Introduction to CMOS VLSI Design Lecture 1A: Manufacturing& Layout David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 1 The Manufacturing Process For a great tour through the IC manufacturing
More informationTechnology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS
INTRODUCTION TO Semiconductor Manufacturing Technology SECOND EDITION Hong Xiao TECHNISCHE INFORMATIONSBiBUOTHEK UNIVERSITATSBIBLIOTHEK HANNOVER SPIE PRESS Bellingham,Washington USA Contents Preface to
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 3D Perspective 2 3 Fabrication
More informationMicroelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width
Microelectronics Introduction to the IC technology M.Rencz 11 September, 2002 9/16/02 1/37 Integrated circuits Development is controlled by the roadmaps. Self-fulfilling predictions for the tendencies
More informationChapter 2 Problems. The CMOS technology we need to realize is shown below, from Figure 1-34 in the text. S P + N P + N WELL P +
Chapter 2 roblems 2.1 Sketch a process flow that would result in the structure shown in Figure 1-34 by drawing a series of drawings similar to those in this chapter. You only need to describe the flow
More informationChapter 2 Manufacturing Process
Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS
More informationCMOS VLSI Design. Introduction. All materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN. Introduction
CMOS VLSI Design Introduction ll materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN Introduction Chapter previews the entire field, subsequent chapters elaborate on specific
More informationSemiconductor Manufacturing Technology. IC Fabrication Process Overview
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you
More informationProblem 1 Lab Questions ( 20 points total)
Problem 1 Lab Questions ( 20 points total) (a) (3 points ) In our EE143 lab, we use Phosphorus for the source and drain diffusion. However, most advanced processes use Arsenic. What is the advantage of
More informationLecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther
EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography
More informationUT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules
2. CMOS Fabrication, Layout, Design Rules Last module: Introduction to the course How a transistor works CMOS transistors This module: CMOS Fabrication Design Rules CMOS Fabrication CMOS transistors are
More informationProcess Flow in Cross Sections
Process Flow in Cross Sections Process (simplified) 0. Clean wafer in nasty acids (HF, HNO 3, H 2 SO 4,...) --> wear gloves! 1. Grow 500 nm of SiO 2 (by putting the wafer in a furnace with O 2 2. Coat
More informationMicrofabrication of Integrated Circuits
Microfabrication of Integrated Circuits OUTLINE History Basic Processes Implant; Oxidation; Photolithography; Masks Layout and Process Flow Device Cross Section Evolution Lecture 38, 12/05/05 Reading This
More informationFABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS
AND FABRICATION ENGINEERING ATTHE MICRO- NANOSCALE Fourth Edition STEPHEN A. CAMPBELL University of Minnesota New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Preface xiii prrt i OVERVIEW AND MATERIALS
More informationIsolation Technology. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041
More informationVLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris
VLSI Lecture 1 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Based on slides of David Money Harris Goals of This Course Learn the principles of VLSI design Learn to design
More informationVLSI Technology. By: Ajay Kumar Gautam
By: Ajay Kumar Gautam Introduction to VLSI Technology, Crystal Growth, Oxidation, Epitaxial Process, Diffusion Process, Ion Implantation, Lithography, Etching, Metallization, VLSI Process Integration,
More informationLecture #18 Fabrication OUTLINE
Transistors on a Chip Lecture #18 Fabrication OUTLINE IC Fabrication Technology Introduction the task at hand Doping Oxidation Thin-film deposition Lithography Etch Lithography trends Plasma processing
More informationLecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1
Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 LECTURE 030 INTEGRATED CIRCUIT TECHNOLOGY - I (References [7,8]) Objective The objective of this presentation is: 1.) Illustrate integrated
More informationChapter 2 MOS Fabrication Technology
Chapter 2 MOS Fabrication Technology Abstract This chapter is concerned with the fabrication of metal oxide semiconductor (MOS) technology. Various processes such as wafer fabrication, oxidation, mask
More informationINTEGRATED-CIRCUIT TECHNOLOGY
INTEGRATED-CIRCUIT TECHNOLOGY 0. Silicon crystal growth and wafer preparation 1. Processing Steps 1.1. Photolitography 1.2. Oxidation 1.3. Layer Deposition 1.4. Etching 1.5. Diffusion 1.6 Backend: assembly,
More informationECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 7: CMOS Manufacturing Process Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last
More informationInstructor: Dr. M. Razaghi. Silicon Oxidation
SILICON OXIDATION Silicon Oxidation Many different kinds of thin films are used to fabricate discrete devices and integrated circuits. Including: Thermal oxides Dielectric layers Polycrystalline silicon
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Processing Technology Topics CMOS Processing Technology Semiconductor Processing How do we make a transistor? Fabrication Process Wafer Processing Silicon single crystal
More informationProcess Integration. MEMS Release Techniques Sacrificial Layer Removal Substrate Undercut
Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap MEMS Release Techniques
More informationFABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag
FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules EE 432 VLSI Modeling and Design 2 CMOS Fabrication
More informationChapter 4 : ULSI Process Integration (0.18 m CMOS Process)
Chapter : ULSI Process Integration (0.8 m CMOS Process) Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e)
More informationLow Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 02 MOS Transistors - I Hello and welcome to today
More informationComplexity of IC Metallization. Early 21 st Century IC Technology
EECS 42 Introduction to Digital Electronics Lecture # 25 Microfabrication Handout of This Lecture. Today: how are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other
More informationPhysics and Material Science of Semiconductor Nanostructures
Physics and Material Science of Semiconductor Nanostructures PHYS 570P Prof. Oana Malis Email: omalis@purdue.edu Today Bulk semiconductor growth Single crystal techniques Nanostructure fabrication Epitaxial
More informationDepartment of Electrical Engineering. Jungli, Taiwan
Chapter 3 Fabrication of CMOS Integrated Circuits Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Background Outline The CMOS Process Flow Design Rules Latchup
More informationIC Fabrication Technology Part III Devices in Semiconductor Processes
EE 330 Lecture 10 IC Fabrication Technology Part III Metalization and Interconnects Parasitic Capacitances Back-end Processes Devices in Semiconductor Processes Resistors Diodes Review from Last Lecture
More informationReview of CMOS Processing Technology
- Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from
More informationPHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam
PHYS 534 (Fall 2008) Process Integration Srikar Vengallatore, McGill University 1 OUTLINE Examples of PROCESS FLOW SEQUENCES >Semiconductor diode >Surface-Micromachined Beam Critical Issues in Process
More informationIC/MEMS Fabrication - Outline. Fabrication
IC/MEMS Fabrication - Outline Fabrication overview Materials Wafer fabrication The Cycle: Deposition Lithography Etching Fabrication IC Fabrication Deposition Spin Casting PVD physical vapor deposition
More informationSemiconductor Technology
Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................
More informationMake sure the exam paper has 9 pages total (including cover page)
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2010 EE143 Midterm Exam #2 Family Name First name SID Signature Solution Make sure the exam
More informationChapter 4. UEEP2613 Microelectronic Fabrication. Oxidation
Chapter 4 UEEP2613 Microelectronic Fabrication Oxidation Prepared by Dr. Lim Soo King 24 Jun 2012 Chapter 4...113 Oxidation...113 4.0 Introduction... 113 4.1 Chemistry of Silicon Dioxide Formation... 115
More informationECE321 Electronics I
ECE321 Electronics I Lecture 19: CMOS Fabrication Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Miller Effect Interconnect
More informationCS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing
CS/ECE 5710/6710 CMOS Processing Addison-Wesley N-type Transistor D G +Vgs + Vds S N-type from the top i electrons - Diffusion Mask Mask for just the diffused regions Top view shows patterns that make
More informationLect. 2: Basics of Si Technology
Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters
More informationSchematic creation of MOS field effect transistor.
Schematic creation of MOS field effect transistor. Gate electrode Drain electrode Source electrode Gate oxide Gate length Page 1 Step 0 The positively doped silicon wafer is first coated with an insulating
More informationTOWARD MEMS!Instructor: Riadh W. Y. Habash
TOWARD MEMS!Instructor: Riadh W. Y. Habash Students are presented with aspects of general production and manufacturing of integrated circuit (IC) products to enable them to better liaise with and participate
More informationChapter 5 Thermal Processes
Chapter 5 Thermal Processes 1 Topics Introduction Hardware Oxidation Diffusion Annealing Post-Implantation Alloying Reflow High Temp CVD Epi Poly Silicon Nitride RTP RTA RTP Future Trends 2 Definition
More informationEE 330 Lecture 8. IC Fabrication Technology Part II. - Masking - Photolithography - Deposition - Etching - Diffusion
EE 330 Lecture 8 IC Fabrication Technology Part II?? - Masking - Photolithography - Deposition - Etching - Diffusion Review from Last Time Technology Files Provide Information About Process Process Flow
More informationECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:
ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline: Fabrication of p-n junctions Contact Potential Things you should know when you leave Key Questions What are the necessary steps to fabricate
More informationMOS Front-End. Field effect transistor
MOS Front-End Back-end Transistor Contact Front-end p-well STI n-well Front-end-of-line includes substrate, isolation, wells, transistor, silicide Field effect transistor MOSFET: Metal-Oxide-Semiconductor
More informationMicrostructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley
Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2 Crystallographic
More informationSemiconductor Device Fabrication
5 May 2003 Review Homework 6 Semiconductor Device Fabrication William Shockley, 1945 The network before the internet Bell Labs established a group to develop a semiconductor replacement for the vacuum
More informationMostafa Soliman, Ph.D. May 5 th 2014
Mostafa Soliman, Ph.D. May 5 th 2014 Mostafa Soliman, Ph.D. 1 Basic MEMS Processes Front-End Processes Back-End Processes 2 Mostafa Soliman, Ph.D. Wafers Deposition Lithography Etch Chips 1- Si Substrate
More informationAjay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University
2014 Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University Page1 Syllabus UNIT 1 Introduction to VLSI Technology: Classification of ICs, Scale of integration,
More informationCMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI
CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters
More informationCMOS Manufacturing process. Design rule set
CMOS Manufacturing process Circuit design Set of optical masks Fabrication process Circuit designer Design rule set Process engineer All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital
More informationProcess Integration. NMOS Generic NMOS Process Flow. CMOS - The MOSIS Process Flow
Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap MEMS Release Techniques
More informationEE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing
3. Conventional licon Processing Micromachining, Microfabrication. EE 5344 Introduction to MEMS CHAPTER 3 Conventional Processing Why silicon? Abundant, cheap, easy to process. licon planar Integrated
More informationOxidation SMT Yau - 1
Oxidation Yau - 1 Objectives After studying the material in this chapter, you will be able to: 1. Describe an oxide film for semiconductor manufacturing, including its atomic structure, how it is used
More informationFABRICATION of MOSFETs
FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the
More informationMark T. Bohr Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration INTEL CORPORATION
Mark T. Bohr Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration INTEL CORPORATION Patents» 6762464, N-P butting connections on SOI substrates, 7/13/2004.»
More informationChemical Vapor Deposition
Chemical Vapor Deposition ESS4810 Lecture Fall 2010 Introduction Chemical vapor deposition (CVD) forms thin films on the surface of a substrate by thermal decomposition and/or reaction of gas compounds
More informationIsolation of elements
1 In an IC, devices on the same substrate must be isolated from one another so that there is no current conduction between them. Isolation uses either the junction or dielectric technique or a combination
More informationSilicon Wafer Processing PAKAGING AND TEST
Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)
More informationUNIT 4. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun
UNIT 4 By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun Syllabus METALLIZATION: Applications and choices, physical vapor deposition, patterning, problem areas.
More informationEE 5611 Introduction to Microelectronic Technologies Fall Tuesday, September 02, 2014 Lecture 01
EE 5611 Introduction to Microelectronic Technologies Fall 2014 Tuesday, September 02, 2014 Lecture 01 1 Instructor: Jing Bai Contact Email: jingbai@d.umn.edu, hone: (218)726-8606, Office: MWAH 255 Webpage:
More informationEE 5611 Introduction to Microelectronic Technologies Fall Tuesday, September 04, 2012 Lecture 01
EE 5611 Introduction to Microelectronic Technologies Fall 2012 Tuesday, September 04, 2012 Lecture 01 1 Instructor: Jing Bai Contact Email: jingbai@d.umn.edu, hone: (218)726-8606, Office: MWAH 255 Webpage:
More information9/4/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter II CMOS Manufacturing Process 1 Dual-Well Trench-Isolated CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 p-well poly n-well SiO 2 n+ p-epi p+ p+ 2 Schematic Layout
More informationEE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania
1 EE 560 FABRICATION OF MOS CIRCUITS 2 CMOS CHIP MANUFACTRING STEPS Substrate Wafer Wafer Fabrication (diffusion, oxidation, photomasking, ion implantation, thin film deposition, etc.) Finished Wafer Wafer
More informationSilicon Manufacturing
Silicon Manufacturing Group Members Young Soon Song Nghia Nguyen Kei Wong Eyad Fanous Hanna Kim Steven Hsu th Fundamental Processing Steps 1.Silicon Manufacturing a) Czochralski method. b) Wafer Manufacturing
More informationVLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 33 Problems in LOCOS + Trench Isolation and Selective Epitaxy So, we are discussing
More informationEE6303 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS 2 MARK QUESTIONS WITH ANSWERS UNIT I IC FABRICATION
SRI VENKATESWARA COLLEGE OF ENGINEERING AND TECHNOLOGY TIRUPACHUR DEPARTMENT OFELECTRICAL AND ELECTRONICS ENGINEERING EE6303 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS 1. Define an Integrated circuit.
More informationIntel Pentium Processor W/MMX
Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:
More informationEE 330 Lecture 12. Devices in Semiconductor Processes
EE 330 Lecture 12 Devices in Semiconductor Processes Review from Lecture 9 Copper Interconnects Limitations of Aluminum Interconnects Electromigration Conductivity not real high Relevant Key Properties
More informationEE 330 Fall Ruden Michael. Al Kaabi Humaid. Archer Tyler. Hafeez Mustafa. Mullen Taylor. Thedens Peter. Cao Khoi.
1 2 5 6 3 4 8 7 1 2 3 4 5 6 ROW EE 330 Fall 2017 9 10 Al Kaabi Humaid Alegria Francisco Allison Trenton Alva Caroline Archer Tyler Bahashwan Abdullah Betke Jarrett Chun Junho Davidson Caleb Faronbi Matthew
More information3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005
3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005 1) This is an open book, take-home quiz. You are not to consult with other class members or anyone else. You may discuss the
More informationVLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 36 MOSFET I Metal gate vs self-aligned poly gate So far, we have discussed about
More information