Electroless CoWP Boosts Copper Reliability, Device Performance Bill Lee, Blue29, Sunnyvale, Calif. -- 7/1/2004 Semiconductor International

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1 <<< Back Print Electroless CoWP Boosts Copper Reliability, Device Performance Bill Lee, Blue29, Sunnyvale, Calif. -- 7/1/2004 Semiconductor International The copper damascene process is widely established and has brought higher performance to semiconductor devices. Copper has replaced aluminum because of its lower resistivity and higher reliability, which was expected to be better because of its higher activation energy for diffusion. However, copper still suffers from electromigration (EM) and stress migration (SM) reliability issues (Fig. 1 ) as geometries continue to shrink, and current densities increase. 1-4 Also, interlevel dielectric (ILD) materials change at the 65 and 45 nm technology nodes. At a Glance Electroless cobalt tungsten phosphide (CoWP) development for 65 and 45 nm deployment is underway. Alkali metal-free chemicals and high-throughput production tools for deposition and metrology are now available, enabling CoWP to overcome interconnect reliability obstacles and provide performance improvements. Electromigration and stress migration In the copper damascene process, the copper line is encapsulated on the sides and bottom by barrier metal, and on top by barrier/etch stop dielectric. The copper/ dielectric interface has weaker adhesion than the copper/barrier metal interface, so copper diffusion occurs predominantly at the top surface. Under high current densities, copper atoms move in the direction of the electron flow, and vacancies accumulate in the opposite direction into voids that cause the device to fail (Fig. 2). Attempts to improve copper/dielectric adhesion using various surface treatments prior to dielectric deposition provide some near-term relief, but ultimately this interface must be fundamentally changed, otherwise current densities will be restricted to the low 10 6 A/cm 2 regime. At 65 nm and future technology nodes, this means drive currents must be lower or interconnect linewidths and via sizes larger, making devices bigger, more expensive and slower. (1 of 7)1/1/2005 7:29:18 AM

2 1. As these void samples show, copper still suffers from electromigration and stress migration as geometries continue to shrink. 2. Electromigration void formation can result as a consequence of the electron flow, and cause device failure. Copper lines have different linewidths on different levels. Vias contacting wide lines above or below (2 of 7)1/1/2005 7:29:18 AM

3 experience void formation in the wide lines caused by thermal stress cycling during wafer manufacturing. 5 Vacancies, which are induced during copper grain growth, move along near grain boundaries and weak interfaces, accumulating at low stress points at the narrower vias (Fig. 3 ). Even narrow lines connecting vias can experience stress-induced voiding if the linewidth increases nearby on the same level Grain growth and weak interfaces can create stress-induced void formation in or near vias. CoWP cap Engineers have successfully solved these reliability problems by adding a cobalt tungsten phosphide (CoWP) cap to the copper using a selective electroless deposition process after CMP Electroless CoWP deposition is self-aligned to copper and forms a smooth conformal film (Fig. 4 ). Depending on process conditions, this layer can be amorphous or pseudo-epitaxial to follow the underlying copper grain structure. The film is typically 90% cobalt in nanocrystalline form with 2% tungsten and 8% phosphorus. 13 The tungsten and phosphide stuff the cobalt grain boundaries, while the cobalt forms the majority of the interface to copper, forming metal-metal 4. Electroless CoWP deposition is selfaligned to copper, resulting in smooth conformal films. The SEM and TEM show a CoWP cap on copper. bonds with adhesion energies above 40 J/m 2, compared with metal-dielectric bonds of J/m 2. Experimentally, Ta/TaN cap and CVD tungsten metal caps have also demonstrated EM lifetime improvements. Electroless deposition has the advantage of being selective to the copper surface, which avoids an expensive patterning step (wet etch to recess the copper, PVD Ta/TaN, second CMP step to remove the Ta/TaN from the ILD surface). Also, compared with CVD tungsten, selectivity is easier to (3 of 7)1/1/2005 7:29:18 AM

4 maintain using the electroless process. Compared with structures using the conventional dielectric layer alone, EM lifetime improvements of one to two orders of magnitude have been demonstrated using a CoWP cap (Table ) Stress migration can also be significantly improved. 7 'Low-k metal' Using a CoWP cap to improve device reliability is a necessity for many chipmakers, while others see it as a way to improve device performance by reducing the effective dielectric constant (k eff ) around the copper lines. The use of a top metal cap that also acts as a copper diffusion barrier allows the dielectric barrier to be eliminated, if its simultaneous use as an etch-stop for the via etch can be obviated. RC time constant reductions of 5-15% are anticipated. 8,11 This can be equivalent to a whole generation of low-k material improvement; e.g., moving from k=2.5 to k=2.1. Key film requirements CoWP thickness requirement is typically in the Å range with a within-wafer non-uniformity of <5% 1s and a wafer-to-wafer non-uniformity of <5% 1σ (for such a thin film, this translates to a few monolayers of variability). EM improvement is relatively independent of thickness, while SM improvement scales with thickness. Thickness is usually limited by line-to-line spacing because the CoWP cap grows isotropically on the copper, so beyond the thickness of the barrier metal, further lateral growth would narrow the spacing and potentially increase line-to-line leakage. Process selectivity is checked with line-to-line leakage. Typically, the new process with CoWP cap must pass the same leakage requirement as the dielectric-capped process. This is dependent on the company, technology and process generation. End-to-end resistance change must be 5%. This includes contributions from line and via resistance, from both dimensional changes and CoWP material resistivity. For the line, the addition of the CoWP cap provides a shunt path for the current, which is useful for overcoming current crowding problems at the vias. While selectivity is critical, care must be taken in the CoWP deposition process so as not to impact the copper thickness, which can negatively affect the final line resistance. For the via, resistance change will depend on whether the CoWP layer is retained or etched through during via etch. The former has the advantage of replacing a weaker TaN/Cu interface with a stronger CoWP/Cu one, but also the disadvantage of putting higher-resistivity (albeit very thin) material in the current path. To ameliorate this issue, cap material resistivity is usually required to be <50 µω-cm. (4 of 7)1/1/2005 7:29:18 AM

5 For each device generation, geometries shrink by ~0.7 in linewidth, or about half in cross-sectional area. Since currents remain approximately constant, current density, j, can as much as double, affecting reliability. According to Black's Law, EM lifetime (MTTF) is inversely proportional to j n, where n varies between 1 and 2 depending on the mode of failure (during void formation or void growth). Thus, lifetime can decrease four times for each technology generation, so 4 is usually stated as the minimum lifetime improvement required and more typically 10 is specified. SM lifetime improvement requirement varies by IC manufacturer. Equation 1 When the focus is on performance improvement through k eff reduction, another requirement is for the metal cap to act as a diffusion barrier. The criteria for this can vary widely. A typical method is to test annealed blanket films of cap metal on copper by surface analysis techniques such as Auger, XPS or Surface SIMS to check for copper. Another is to build an MIM capacitor stack with the bottom metal electrode capped, and check the C-V properties after anneal for any copper in the dielectric. Processing requirements Electroless CoWP deposition selectivity requires the surface of the copper and ILD to be very clean. For example, any post-cmp passivation material such as BTA must be removed from the copper surface, and all unwanted foreign matter has to be removed from the ILD surface (including any embedded copper atoms). Sometimes an activation step is used to improve copper's catalytic nature. After CoWP deposition, further surface treatment may be used to prepare for the next step in the integration flow. All told, this may involve two to five chemicals that the hardware should handle in an easily programmable and cost-effective manner. Some of the chemical formulations perform best at high temperatures near their boiling points. For example, film growth incubation time falls below 1 sec above 90 C, which helps achieve thin conformal films with full coverage while also improving throughput. This necessitates that the hardware support this by preventing evaporation losses of volatile chemical components, which would change the solution composition and process performance. The focus in this application is to make the highest-quality interface between the copper and CoWP. Once the copper surface is cleaned it should not be allowed to deteriorate before the CoWP cap is deposited. Conventional plating systems that transfer wafers between chemical baths or spray stations expose the wafers to air. Since each chemical processing step requires different amounts of time, queue times between steps allow the copper surface to oxidize. Partial drying of the wafer surface while waiting can also cause non-uniform CoWP nucleation and film growth. Therefore, the hardware for electroless processes should be designed to have minimal queue time between steps while keeping the wafer surface wet and in a nonoxidizing environment. Electroless deposition relies on the interaction of several components in solution, which should be monitored and adjusted as necessary in real time. Optical methods such as UV-VIS and Raman spectroscopy are preferred because they are non-invasive and can monitor multiple components simultaneously. Chemical analysis methods such as ion chromatography are useful for development, but best performed offline (per (5 of 7)1/1/2005 7:29:18 AM

6 shift qualification, for example) in production. The cost of adding the CoWP layer must be as low as possible. This generally comes down to depreciation and chemical costs, since consumables are few. Depreciation can be minimized if throughput is high. Chemical cost can be reduced over time as per-wafer chemical usage is reduced, and formulations changed to lower-cost alloys. Metrology Measuring a 100 Å thickness with sufficient precision to check 5% non-uniformity with a patterned film is not trivial. For blanket films, the metal cap layer is thin enough to enable spectroscopic ellipsometry to work at the shorter wavelengths. But for patterned wafers, a smaller spot size is required. For ternary alloys, it is also useful to measure film composition simultaneously. For example, P% can affect film stress and the ratio of W% and P% to Co% can affect its copper diffusion barrier property. Electron-stimulated X-ray analysis can yield both thickness and composition information (Fig. 5 ). For closed-loop control, optical methods such as spectrophotometry can be used for integrated thickness monitoring on the deposition system. 5. Simultaneous thickness and composition can be determined through electron-stimulated X- ray analysis. (Source: KLA-Tencor) Summary Development of electroless CoWP technology for 65 and 45 nm deployment is underway at the leading IC companies. Alkali metal-free semiconductor-grade chemicals, and high-throughput production tools for deposition and metrology are now available. CoWP will allow the semiconductor industry to overcome interconnect reliability obstacles and provide performance improvements by alleviating the use of materials that increase k eff of the ILD. (6 of 7)1/1/2005 7:29:18 AM

7 Author Information Bill Lee is director of marketing at Blue29. He has worked with PVD, CVD and etch systems at Applied Materials, and with e-beam metrology systems at Schlumberger. He has an M.S. EECS from the Massachusetts Institute of Technology, and an M.B.A. from Stanford University. References 1. P. Singer, "Copper Challenges for the 45nm Node," Semiconductor International, May 2004, p L. Peters, "Low-k Dielectrics Pose New Reliability Concerns," Semiconductor International, February 2003, p L. Peters, "Exploring Advanced Interconnect Reliability," Semiconductor International, July 2002, p K.N. Tu., "Recent Advances on Electromigration in Very Large-Scale Integration of Interconnects," Journal of Applied Physics, 2003, Vol. 94, No. 9, p T. Oshima, et al., "Suppression of Stress-Induced Voiding in Copper Interconnects," Proc. IEDM, K. Yoshida, et al., "Stress-Induced Voiding Phenomena for Actual CMOS LSI Interconnects," Proc. IEDM, T. Ishigami, et al., "High Reliability Cu Interconnection Utilizing a Low Contamination CoWP Capping Layer," Proc. IITC, P. Moon, et al., "Process Roadmap and Challenges for Metal Barriers," Proc. IEDM, C.K. Hu, et al., "Reduced Cu Interface Diffusion by CoWP Surface Coating," Microelectronic Engineering, C.K. Hu, et al., "Effects of Overlayers on Electromigration Reliability Improvements for Cu/Low k Interconnects," Proc. IRPS, T. Ko, et al., "High Performance/Reliability Cu Interconnect with Selective CoWP Cap," Symposium on VLSI Technology, E.J. O'Sullivan, et al., "Electrolessly Deposited Diffusion Barriers for Microelectronics," IBM Jour. of R&D, 1998, Vol. 42, No. 5, p A. Kohn, et al., "Characterization of Electroless Deposited Co(W,P) Thin Films for Encapsulation of Copper Metallization," Materials Science and Engineering, 2001, Vol. A302, p. 18. <<< Back Print 2005, Reed Business Information, a division of Reed Elsevier Inc. All Rights Reserved. (7 of 7)1/1/2005 7:29:18 AM