EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Transcription

1 Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/ mm Fab Tour Overview of IC Technology Slide 1

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3 45 1µm = 10-4 cm = 10-6 m = 1000 nm nm n + n + Micron and Nanometer State-of-the-art transistor in mass production ~ 500 Transistors Diameter of human hair ~50µm 3 Slide 3

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6 Perspective on Moore s Law In 2005, cost of a transistor = cost of printing one letter in NY Times we are already producing transistors per year. Enough to supply every ant on the planet with ten transistors. Twenty years from now, if the trend continues, there will be more transistors than there will be cells in the total number of human bodies on Earth. Slide 6

7 Chip Power consumption is a big concern!!!! 7 Slide 7 Source: Intel Developer Forum 2002

8 Integrated Circuit Fabrication Goal: Mass fabrication (i.e. simultaneous fabrication) of many chips, each a circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors Planar Technology Slide 8

9 The Chip Making Process Slide 9

10 Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer Slide 10 10

11 Adding Dopants into Si Suppose we have a wafer of Si which is p-type and we want to change the surface to n-type. The way in which this is done is by ion implantation. Dopant ions are shot out of an ion gun called an ion implanter, into the surface of the wafer. Eaton HE3 High-Energy Implanter, showing the ion beam hitting the end-station x + As + or P + or B + ions SiO 2 Si Typical implant energies are in the range kev. After the ion implantation, the wafers are heated to a high temperature (~1000 o C). This annealing step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites. Slide 11

12 Dopant Diffusion The implanted depth-profile of dopant atoms is peaked. dopant atom concentration (logarithmic scale) as-implanted profile depth, x In order to achieve a more uniform dopant profile, hightemperature annealing is used to diffuse the dopants Dopants can also be directly introduced into the surface of a wafer by diffusion (rather than by ion implantation) from a dopant-containing ambient or doped solid source Slide 12

13 Rapid Thermal Annealing (RTA) Sub-micron MOSFETs need ultra-shallow junctions (x j <50 nm) Dopant diffusion during activation anneal must be minimized Short annealing time (<1 min.) at high temperature is required Ordinary furnaces (e.g. used for thermal oxidation and CVD) heat and cool wafers at a slow rate (<50 o C per minute) Special annealing tools have been developed to enable much faster temperature ramping, and precise control of annealing time ramp rates as fast as 200 o C/second anneal times as short as 0.5 second typically single-wafer process chamber: Slide 13

14 Rapid Thermal Annealing Tools There are 2 types of RTA systems: 1. Furnace-based steady heat source + fast mechanical wafer transport 2. Lamp-based stationary wafer + time-varying optical output from lamp(s) Furnace RTA Lamp RTA A.T. Fiory, Proc. RTP2000 Slide 14

15 Formation of Insulating Films The favored insulator is pure silicon dioxide (SiO 2 ). A SiO 2 film can be formed by one of two methods: 1. Oxidation of Si at high temperature in O 2 or steam ambient 2. Deposition of a silicon dioxide film ASM A412 batch oxidation furnace Applied Materials lowpressure chemical-vapor deposition (CVD) chamber Slide 15

16 Thermal Oxidation Si + O 2 SiO 2 or Si + 2H O + H 2 SiO2 2 2 dry oxidation wet oxidation Temperature range: 700 o C to 1100 o C Process: O 2 or H 2 O diffuses through SiO 2 and reacts with Si at the interface to form more SiO 2 1 µm of SiO 2 formed consumes ~0.5 µm of Si oxide thickness t time, t t Slide 16

17 Physical Vapor Deposition ( Sputtering ) Used to deposit Al films: Highly energetic argon ions batter the surface of a metal target, knocking atoms loose, which then land on the surface of the wafer Sometimes the substrate is heated, to ~300 o C Al Ar + Al I Ar + Al Negative Bias ( kv) Al target wafer Ar plasma Al film Gas pressure: 1 to 10 mtorr Deposition rate I S Slide 17 ion current sputtering yield

18 Chemical Vapor Deposition (CVD) of Si Polycrystalline silicon ( poly-si ): Like SiO 2, Si can be deposited by Chemical Vapor Deposition: Wafer is heated to ~600 o C Silicon-containing gas (SiH 4 ) is injected into the furnace: SiH = 4 Si + 2H 2 Si film made up of crystallites SiO 2 Silicon wafer Properties: sheet resistance (heavily doped, 0.5 µm thick) = 20 Ω/ can withstand high-temperature anneals major advantage Slide 18

19 Conformality CVD Properties: Can be deposited on top of anything. Can follow ups & downs (topography) of pre-existing layers Slide 19

20 The Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating photoresist exposure process step spin, rinse, dry acid etch photoresist develop Slide 20

21 Photoresist Exposure A glass mask with a black/clear pattern is used to expose a wafer coated with ~1 µm thick photoresist UV light Mask Lens Image of mask appears here (3 dark areas, 4 light areas) photoresist Si wafer Smallest feature size printable photon wavelength λ Areas exposed to UV light are susceptible to chemical removal Slide 21

22 Photoresist Development Solutions with high ph dissolve the areas which were exposed to UV light; unexposed areas are not dissolved Exposed areas of photoresist Developed photoresist Slide 22

23 Exposure using Stepper Tool scribe line field size increases with technology generation images 1 2 wafer Translational motion Slide 23

24 Importance of Layer-to-Layer Alignment Example: metal line (blue) to contact hole (black) marginal contact Top View no contact! Metal line is bigger than contact hole for safety margin to allow for misalignment Design Rules are needed: Slide 24

25 Photo Lithography Trends Lithography determines the minimum feature size and limits the throughput that can be achieved in an IC manufacturing process. Thus, lithography research & development efforts are directed at 1. achieving higher resolution shorter wavelengths 365 nm 248 nm 193 nm 13 nm i-line DUV EUV 2. improving resist materials higher sensitivity, for shorter exposure times (throughput target is 60 wafers/hr) Slide 25

26 Pattern Transfer by Etching Selective etch processes (using plasma or aqueous chemistry) have been developed for most IC materials First: pattern photoresist Next: Etch oxide Si photoresist SiO 2 We have exposed mask pattern, and developed the resist oxide etchant photoresist is resistant. etch stops on silicon ( selective etchant ) Last: strip resist only resist is attacked Slide 26

27 Dry Etching vs. Wet Etching Pattern resist mask Etching thin film Etching completed Remove resist mask Processing Temperature Ambient Anisotropic (e.g. Reactive Ion Etching) Isotropic (e.g. Wet Etching) Slide 27 27

28 Multilevel Metallization Via Interconnect Slide 28

29 Chemical Mechanical Polishing (CMP) Chemical mechanical polishing is used to planarize the surface of a wafer at various steps in the process of fabricating an integrated circuit. interlevel dielectric (ILD) layers shallow trench isolation (STI) copper metallization damascene process IC with 5 layers of Al wiring Oxide Isolation of Transistors p+ n p+ SiO 2 n+ p n+ p Slide 29

30 CMP Tool Wafer is polished using a slurry containing silica particles (10-90nm particle size) chemical etchants (e.g. HF) Slide 30

31 Copper Metallization Dual Damascene Process (IBM Corporation) (1) courtesy of Sung Gyu Pyo, Hynix Semiconductor (2) (4) (3) (5) Slide 31

32 CMOS Technology Challenge: Build both NMOS & PMOS transistors on a single silicon chip NMOSFETs need a p-type substrate PMOSFETs need an n-type substrate Requires extra process steps! p+ p+ oxide n+ n+ n-type Si p-well Slide 32

33 n-type wafer *Create p-well Grow thick oxide Slide 33 oxide *Remove thick oxide in transistor areas ( active region ) Grow gate oxide Deposit & *pattern poly-si gate electrodes *Dope n channel source and drains (need to protect PMOS areas) *Dope p-channel source and drains (need to protect NMOS areas) Deposit insulating layer (oxide) *Open contact holes Conceptual CMOS Process Flow p+ p+ Deposit and *pattern metal interconnects n-type Si n+ n+ p-well At least 3 more masks, as compared to NMOS process

34 Additional Process Steps Required for CMOS 1. Well Formation Top view of p-well mask (dark field) Cross-sectional view of wafer boron p-well SiO 2 n-type Si Before transistor fabrication, we must perform the following process steps: 1. grow oxide layer; pattern oxide using p-well mask 2. implant phosphorus; anneal to form deep p-type regions Slide 34

35 2. Masking the Source/Drain Implants Select p-channel Select n-channel We must protect the n-channel devices during the boron implantation step, and We must protect the p-channel devices during the arsenic implantation step Example: Select p-channel boron p+ p+ oxide photoresist n+ n+ n-type Si p-well Slide 35

36 Forming Body Contacts Modify oxide mask and select masks: 1. Open holes in original oxide layer, for body contacts 2. Include openings in select masks, to dope these regions n+ oxide p+ p+ n+ n+ p+ p-well n-type Si Slide 36

37 Select Masks N-select: n+ oxide n-type Si n+ n+ p-well P-select: n+ oxide p+ p+ n+ n+ p+ p-well n-type Si Slide 37

38 Visualizing Layouts and Cross-Sections with SIMPLer SIMPL is a CAD tool created by Prof. Neureuther s group of UCB allows IC designers to visualize device cross-sections corresponding to a fabrication process and physical layout. You can access SIMPLat Slide 38

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