VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

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1 VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)

2 contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ωo ; Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters. 2

3 The First Computer The Babbage Difference Engine (1832) 25,000 parts cost: 17,470 3

4 ENIAC - The first electronic computer (1946) 4

5 WHY VLSI? Integration Improves the Design Lower parasitics, higher clocking speed Lower power Physically small Integration Reduces Manufacturing Costs (almost) no manual assembly About $1-5billion/fab Typical Fab 1 city block, a few hundred people Packaging is largest cost Testing is second largest cost 5

6 Design Levels SYSTEM + MODULE GATE CIRCUIT S n+ G D n+ DEVICE 6

7 Moore s Law Gordon Moore cofounder of Intel Corporation visualized in the 1970 s that chip building technology would improve very quickly He projected that the number of transistors on a chip would double about every 18 months 7

8 INTEGRADED CIRCUIT (IC): Multi terminal electronic device in which discrete components like transistors,resisters,capacitors are fabricated in a single construction process. Classification of ICs : Based on application -Analog, digital Based on complexity -SSI, MSI, LSI, VLSI Based on fabrication-monolithic, hybrid Based on technology -RTL,DTL, TTL, MOS. 8

9 IC Evolution : SSI Small Scale Integration (early 1970s)-contained 1 10 logic gates MSI Medium Scale Integration-logic functions, counters LSI Large Scale Integration-first microprocessors on the chip VLSI Very Large Scale Integration-now offers 64-bit microprocessors, complete with cache memory (L1 and often L2),floating-point arithmetic unit(s), etc. Bipolar technology TTL (transistor-transistor logic) ECL (emitter-coupled logic) 9

10 Metal-oxide-semiconductor (MOS) and related VLSI technology MOS (Metal-oxide-silicon) although invented before bipolar transistor, was initially difficult to manufacture nmos (n-channel MOS) technology developed in 1970s required fewer masking steps, was denser, and consumed less power than equivalent bipolar Ics. CMOS (Complementary MOS): n-channel and p-channel MOS transistors => lower power consumption, simplified fabrication process Bi-CMOS - hybrid Bipolar, CMOS (for high speed) GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF) 10

11 Mos transistors Basic MOS transistors with the doping concentration of transistor two types of MOS transistors are available as NMOS transistor and PMOS transistor. With their mode of operation further they are classified as depletion mode transistor and enhancement mode transistor. nmos enhancement mode transistor nmos devices are formed in a p-type substrate of moderate doping level. The source and drain regions are formed by diffusing n-type impurities through suitable masks into these areas. Thus source and drain are isolated from one another by two diodes and their Connections are made by a deposited metal layer. The basic block diagrams of nmos enhancement mode transistor is shown in figure. 11

nmos enhancement mode transistor nmos depletion mode transistor The basic block diagram of nmos depletion mode transistor is shown in figure.

12 nmos enhancement mode transistor nmos depletion mode transistor The basic block diagram of nmos depletion mode transistor is shown in figure. In depletion mode transistor the channel is established even the voltage Vgs = 0 by implanting suitable impurities in the region between source and drain during manufacture and prior to depositing the insulation and the gate. 12

13 MOS Transistors Four terminal device: gate, source, drain, body Polysilicon SiO 2 Source Gate Drain Gate oxide body stack looks like a capacitor p+ p+ n bulk Si Gate and body are conductors (body is also called the substrate) SiO2 (oxide) is a good insulator (separates the gate from the body Source Gate Drain Polysilicon SiO 2 Called metal oxide semiconductor (MOS) capacitor, even though gate is mostly made of poly-crystalline silicon (polysilicon) n+ p n+ bulk Si NMOS PMOS 13

14 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g = 0 g = 1 nmos g d s d s OFF d s ON pmos g d s d s ON d s OFF 14

15 CMOS Inverter A Y V DD ON A=0 Y=1 A Y OFF GND 15

16 CMOS NAND Gate A B Y Y A B 16

17 CMOS NAND Gate A B Y A=0 ON ON Y=1 OFF 1 1 B=0 OFF 17

18 CMOS NAND Gate A B Y A=0 OFF ON Y=1 OFF 1 1 B=1 ON 18

19 CMOS NAND Gate A B Y A=1 ON OFF Y=1 ON 1 1 B=0 OFF 19

20 CMOS NAND Gate A B Y A=1 OFF OFF Y=0 ON B=1 ON 20

21 CMOS NOR Gate A B Y A B Y 21

22 nmos FABRICATION 22

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24 Photolithographic Process oxidation optical mask photoresist removal (ashing) process step photoresist coating photoresist development stepper exposure 24 spin, rinse, dry acid etch

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26 Complementary MOS fabrication CMOS Technology depends on using both N-Type and P-Type devices on the same chip.the two main technologies to do this task are: P-Well :The substrate is N-Type. The N-Channel device is built into a P-Type well within the parent N-Type substrate. The P-channel device is built directly on the substrate. N-Well:The substrate is P-Type. The N-channel device is built directly on the substrate, while the P-channel device is built into a N-type well within the parent P-Type substrate. Two more advanced technologies to do this task are: Twin Tub:Both an N-Well and a P-Well are manufactured on a lightly doped N-type substrate. Silicon-on-Insulator (SOI) CMOS Process:SOI allows the creation of independent, completely isolated nmos and pmos transistors virtually side-by-side on an insulating substrate. 26

27 What is CMOS? CMOS 27

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33 Start with blank wafer First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 33

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36 Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2 p substrate 36

37 Oxidation Grow SiO2 on top of Si wafer C with H2O or O2 in oxidation furnace SiO 2 p substrate 37

38 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO 2 p substrate 38

39 Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO 2 p substrate 39

40 Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed Photoresist SiO 2 p substrate 40

41 Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn t melt in next step SiO 2 p substrate 41

42 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si SiO 2 n well 42

43 Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps p substrate n well 43

44 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor Polysilicon Thin gate oxide p substrate n well 44

45 Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide p substrate n well 45

46 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nmos source, drain, and n-well contact p substrate n well 46

47 N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn t melt during later processing n+ Diffusion p substrate n well 47

48 N-diffusion Historically dopants were diffused Usually ion implantation today But regions are still called diffusion n+ n+ n+ p substrate n well 48

49 N-diffusion Strip off oxide to complete patterning step n+ n+ n+ p substrate n well 49

50 P-Diffusion Similar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ p substrate n well 50

51 Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed Contact p+ n+ n+ p+ p+ n+ Thick field oxide p substrate n well 51

52 Metallization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires Metal p+ n+ n+ p+ p+ n+ Metal Thick field oxide p substrate n well 52

53 Twin-Tub (Twin-Well) CMOS Process This technology provides the basis for separate optimization of the nmos and pmos transistors, thus making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. Generally, the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics. The Twin-Tub process is shown below. In the conventional p & n-well CMOS process, the doping density of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics. The twin-tub process avoids this problem. 53

54 Advanced CMOS Technologies For inexpensive and low-performance chips, one may use a heavily doped substrate and omit one well. The substrate should be doped to about /cm 3, with a resistivity of about 1 Ω-cm. This allows simpler construction, with good Ground Potential distribution, but the devices are not optimal and there is a chance of latch-up if the voltages are pushed hard. For high-performance chips, one uses a low doped substrate, /cm 3, 10 Ω-cm, and then constructs Two Wells at optimum doping levels (called Tubs in the diagram). Since the substrate is lightly doped, there is less chance for latch-up because of the high resistivity. Substrate for Twin-Well MOS Technogy

55 Self-aligned Twin Well 55 Wafer clean Grow pad oxide Deposit nitride (a) N-well mask Etch nitride Strip photoresist N-well implantation (b) Anneal/drive-in and oxidation (c) Strip nitride P-well implantation (d) Anneal and drive Strip pad oxide (e) (a) (b) (c) (d) (e) Silicon Phosphorus Ions Silicon Silicon Dioxide N-well Silicon Silicon Dioxide N-well Silicon N-well Silicon Nitride Nitride Nitride Boron Ion Implantation P-well

56 Self-aligned Twin Well Advantage: reduce a photo mask step Reduce cost Improve IC chip yield. Disadvantage: wafer surface is not flat n-well always has lower level than p-well Affect photolithography resolution Affect thin film deposition N-well implant first Phosphorus diffuses slower than boron in single silicon If p-well implant first, boron in p-well could diffuse out of control during n-well anneal and drive-in 56

57 Twin Well Two mask steps Flat surface Common used in advanced CMOS IC chip High energy, low current implanters Furnaces annealing and driving-in Phosphorus Ions Boron Ions Photoresist P-Epi N-Well P-Well Photoresist N-Well P-Wafer P-Epi P-Wafer 57

58 Silicon-on-Insulator (SOI) CMOS Process Rather than using silicon as the substrate material, technologists have sought to use an insulating substrate to improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent, completely isolated nmos and pmos transistors virtually side-by-side on an insulating substrate. The main advantages of this technology are the higher integration density (because of the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional p & n-well or twin-tub CMOS processes. A cross-section of nmos and pmos devices using SOI process is shown below. The SOI CMOS process is considerably more costly than the standard p & n-well CMOS process. Yet the improvements of device performance and the absence of latch-up problems can justify its use, especially for deep-sub-micron devices. 58

59 Thank you

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each