INTRODUCTION TO VLSI FABRICATION MATERIALS & PROCESSES. Primary Chip Ingredients

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1 INTRODUCTION TO VLSI FABRICATION MATERIALS & PROCESSES Primary Chi Ingredients 1) Silicon crystalline Near erfect crystal (atoms organized in a regular, ordered lattice) Semiconductor not a conductor or insulator, but somewhere in between and its conduction can be altered significantly 2) Silicon dioxide Just like it says, made from silicon and oxygen Insulator 3) Silicon olycrystalline, oly, olysilicon Silicon but only small regions are organized as crystalline structures. Polysilicon structures are made u of multile small crystalline regions where the smaller regions are not aligned with each other. 4) n tye doants Materials that contain 5 outer electrons donors Examles: hoshorus, arsenic EEC 116, B. Baas 5 1

2 Primary Chi Ingredients 5) tye doants Materials that contain 3 outer electrons accetors Examles: boron, gallium 6) Metal wires In older technologies, made of aluminum. Now coer is commonly used because of its lower resistivity. Conductors 7) Contacts/vias Tungsten and aluminium commonly used These are vertical connections between layers EEC 116, B. Baas 6 Primary Fabrication-Ingredients and Fabrication-Processes 1) Photoresist Positive hotoresist (becomes soluble when exosed to UV light) Negative hotoresist (becomes insoluble when exosed to UV light) Alied roughly 1 μm thick to entire wafer 2) Etching rocesses The selectivity of different etches varies in the sense that the materials that are etched or not etched deends on the articular etch. Acid (wet etching). Ex: HF acid Plasma (dry etching) 3) Masks one er atterned shae Picture a develoed film negative EEC 116, B. Baas 7 2

3 Primary Fabrication-Ingredients and Fabrication-Processes 4) Laying down material A. Deosition Examle method: CVD Examle materials:, silicon B. Growth Examle materials: on silicon C. Imlantation Produces high doant concentration regions Diffusion imlantation Silicon exosed to doant gas at high temerature Ion imlantation Doant ions are imlanted at high seed with an accelerator Causes lattice damage Normally followed by annealing ste (short high temerature crystal healing rocess) Examle imlanted structures: source/drains, transistor channels, well and contacts, olysilicon D. Suttering for metals EEC 116, B. Baas 8 Primary Fabrication Ingredients and Processes 5) Planarization extreme flattening of the wafer s surface Suose we have the case below where similar atterns stacked on to of each other roduce large vertical features Ideal Without lanarization Cracks more easily and has high resistance on vertical ortions EEC 116, B. Baas 9 3

4 Primary Fabrication Ingredients and Processes 5) Planarization extreme flattening of the wafer s surface CMP: Chemical Mechanical Planarization (or Polishing) Needed for reliability and consistent thickness of a large number of interconnect layers Ideal and with CMP rocessing stes Without lanarization EEC 116, B. Baas 10 Basic reeated rocess 1) Deosit a material 2) Coat with hotoresist 3) Exose hotoresist to a attern of UV light using a light source and a atterned mask 4) Remove soluble hotoresist with selective etching 5) Remove material below hotoresist with selective etching (base material only) 6) Remove remaining hotoresist with selective etching (hardened hotoresist only) EEC 116, B. Baas 11 4

5 Photo-Lithograhic Process Overview oxidation otical mask hotoresist removal (ashing) hotoresist coating steer exosure rocess ste Tyical oerations in a single hotolithograhic cycle (from [Fullman]). hotoresist develoment acid etch sin, rinse, dry EEC 116, B. Baas Source: Digital Integrated Circuits, 2nd 12 Etching of Polysilicon EEC 116, B. Baas Source: Device Electronics for Int. Circuits 13 5