4/10/2012. Introduction to Microfabrication. Fabrication

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1 Introduction to Microfabrication Fabrication 1

2 MEMS Fabrication Flow Basic Process Flow in Micromachining Nadim Maluf, An introduction to Microelectromechanical Systems Engineering 2

3 Thin Film Deposition Thin Film Deposition Hiroshi Toshiyoshi, UCLA 3

4 Thin Film Deposition Hiroshi Toshiyoshi, UCLA Thin Film Deposition Hiroshi Toshiyoshi, UCLA 4

5 Photolithography Photoresist Spin Coating R. B. Darling 5

6 Photolithography Nadim Maluf, An introduction to Microelectromechanical Systems Engineering Photolithographic Process 6

7 Photolithographic Process Mask Alignment 7

8 Backside Alignment Nadim Maluf, An introduction to Microelectromechanical Systems Engineering Split Field Alignment R. B. Darling 8

9 Resist Spinner Mask Aligner 9

10 Developer Selective Etching 10

11 Selective Etching Hiroshi Toshiyoshi, UCLA Wet Etch 11

12 Dry Etch Selective Etching Hiroshi Toshiyoshi, UCLA 12

13 Topography Kovacs Surface Topography Nadim Maluf, An introduction to Microelectromechanical Systems Engineering 13

14 Surface Micromachining Sandia SUMMIT 14

15 Electrostatic Comb-Drive Resonators C. Nguyen and R. T. Howe, IEEE IEDM, Washington, D.C., December 1993 Polysilicon Electrostatic Micromotor Self-aligned pin-joint, made possible by conformal deposition of structural and sacrificial layers Prof. Mehran Mehregany, Case Western Reserve Univ. 15

16 Hinged Structures Hinged microstructures Pister K S J, Judy M W, Burgett S R and Fearing R S 1992 Microfabricated hinges Sensors Actuators A Surface Micromachining 16

17 Surface Micromachining Hiroshi Toshiyoshi, UCLA Common Mistakes! 17

18 A Surface Micromachining Process Flow PolyMUMPS About PolyMUMPs PolyMUMPs is a 3-layer polysilicon surface micromachining process The basic process includes 8 lithography levels, and 7 physical layers 2 mechanical (Poly1 and Poly2) and 1 electrical layer of polysilicon (Poly0) 2 sacrificial layers (1 st Oxide, 2 nd Oxide) 1 electrical conduction layer (Metal) 1 electrical isolation layer (Nitride) 18

19 PolyMUMPs Seven Physical Layers Nitride - for isolation between substrate and electrical surface layers (0.6 µm) Poly zero - an electrical poly layer for ground plane or electrode formation (0.5 µm). Below the first mechanical layer First oxide - first sacrificial oxide layer, providing gap (2 µm) between poly1 and substrate/nitride Poly 1 - First mechanical layer (2 µm) Second oxide - second sacrificial oxide layer (0.75 µm), provides gap between second and first polysilicon Poly 2 - Second mechanical layer (1.5 µm) Metal - provides electrical connection to package (0.5 µm) PolyMUMPs Eight Lithography Levels POLY ZERO - defines the polysilicon zero features ANCHOR 1 - opens points-of-contact between first polysilicon and substrate (nitride or poly 0) DIMPLE - generates 'bumps' in under-surface of poly 1 to minimize stiction POLY 1 - defines first polysilicon features POLY1_POLY2_VIA - opens points-of-contact between first and second polysilicon ANCHOR 2 - opens points-of-contact between second polysilicon and substrate/nitride POLY 2 - defines second polysilicon features METAL - defines location of metal features 19

20 Common Layout Terminology Layer a physical layer of material deposited during the fabrication process Always represented in mixed-case letters LEVEL a lithographic level used to pattern a physical layer. It may or may not correspond with a physical layer e.g. poly1= POLY1, but Second oxide is patterned by both ANCHOR2 and POLY1_POLY2_VIA Always represented in CAPITAL letters Common Layout Terminology Dimples small, shallow features in the underside of the lower polysilicon layer to minimize the area of contact between the polysilicon and the substrate CVD: Chemical Vapor Deposition a method of depositing layers of material through the interaction of gases at low vacuum and increased temperature A CVD deposition is generally conformal - follows closely the underlying topography 20

21 Common Layout Terminology PSG: Phospho-silicate-glass a phosphorous containing silicon dioxide layer generated by CVD and used for its fast etching properties Sacrificial oxide a layer of fast etching silicon dioxide used to define the separation between the mechanical layers and the substrate RIE: Reactive Ion Etching a dry physical or chemical etching method which removes specific material through the interaction of gas and plasma with the wafer surface Common Layout Terminology Stringer a ribbon of material left behind after an RIE etch step. Generally created at a topographic edge Lift-off a method of depositing metal which uses a polymer template. The sidewall profile of the polymer is defined such that the continuity of the deposited metal is interrupted by the step, and subsequent insertion into a solvent bath removes the polymer layer and the metal residing upon it 21

22 Common Layout Terminology Release the last step of the process where the sacrificial layers are removed by submersion into HF Stiction the sticking effect between polysilicon and the substrate which occurs during the removal of the sacrificial oxide. Many attempts to limit stiction, including dimples, special release chemicals and processes, are tried, some successfully PolyMUMPs Process FIGURE 1.2. The surface of the starting n-type (100) wafers are heavily doped with phosphorus in a standard diffusion furnace using POCl 3 as the dopant source. A 600 nm blanket layer of low stress silicon nitride (Nitride) is deposited followed by a blanket layer of 500 nm polysilicon (Poly 0). The wafers are then coated with UV-sensitive photoresist. 22

23 PolyMUMPs Process FIGURE 1.3. The photoresist is lithographically patterned by exposing it to UV light through the first level mask (POLY0) and then developing it. The photoresist in exposed areas is removed leaving behind a patterned photoresist mask for etching. PolyMUMPs Process (0.5 µm) FIGURE 1.4. Reactive ion etching (RIE) is used to remove the unwanted polysilicon. After the etch, the photoresist is chemically stripped in a solvent bath. This method of patterning the wafers with photoresist, etching and stripping the remaining photoresist is used repeatedly in the PolyMUMPs process. 23

24 PolyMUMPs Process (2.0 µm) FIGURE 1.5. A 2.0 µm layer of PSG is deposited on the wafers by low pressure chemical vapor deposition (LPCVD). This is the first sacrificial layer. PolyMUMPs Process (0.75 µm) FIGURE 1.6. The wafers are coated with photoresist and the second level (DIMPLE) is lithographically patterned. The dimples, 750 nm deep, are reactive ion etched into the first oxide layer. After the etch, the photoresist is stripped. 24

25 PolyMUMPs Process FIGURE 1.7. The wafers are re-coated with photoresist and the third level (ANCHOR1) is lithographically patterned. The unwanted oxide is removed in an RIE etch and the photoresist is stripped. PolyMUMPs Process (2.0 µm) FIGURE 1.8. A blanket 2.0 µm layer of un-doped polysilicon is deposited by LPCVD followed by the deposition of 200 nm PSG and a 1050 C/1 hour anneal. The anneal serves to both dope the polysilicon and reduce its residual stress. 25

26 PolyMUMPs Process FIGURE 1.9. The wafer is coated with photoresist and the fourth level (POLY1) is lithographically patterned. The PSG is first etched to create a hard mask and then Poly 1 is etched by RIE. After the etch is completed, the photoresist and PSG hard mask are removed. PolyMUMPs Process (0.75 µm) FIGURE The Second Oxide layer, 0.75 µm of PSG, is deposited on the wafer. This layer is patterned twice to allow contact to both Poly 1 and substrate layers. 26

27 PolyMUMPs Process FIGURE The wafer is coated with photoresist and the fifth level (POLY1_POLY2_VIA) is lithographically patterned. The unwanted Second Oxide is RIE etched, stopping on Poly 1, and the photoresist is stripped. PolyMUMPs Process FIGURE The wafer is re-coated with photoresist and the sixth level (ANCHOR2) is lithographically patterned. The Second and First Oxides are RIE etched, stopping on either Nitride or Poly 0, and the photoresist is stripped. The ANCHOR2 level provides openings for Poly 2 to contact with Nitride or Poly 0. 27

28 PolyMUMPs Process (1.5 µm) FIGURE A 1.5 µm un-doped polysilicon layer is deposited followed by a 200 nm PSG hardmask layer. The wafers are annealed at 1050 C for one hour to dope the polysilicon and reduce residual stress. PolyMUMPs Process FIGURE The wafer is coated with photoresist and the seventh level (POLY2) is lithographically patterned. The PSG hard mask and Poly 2 layers are RIE etched and the photoresist and hard mask are removed. All mechanical structures have now been fabricated. The remaining steps are to deposit the metal layer and remove the sacrificial oxides. 28

29 PolyMUMPs Process (0.5 µm) FIGURE The wafer is coated with photoresist and the eighth level (METAL) is lithographically patterned. The metal (gold with a thin adhesion layer) is deposited by lift-off patterning which does not require etching. The side wall of the photoresist is sloped at a reentrant angle, which allows the metal to be deposited on the surfaces of the wafer and the photoresist, but provides breaks in the continuity of the metal over the reentrant photoresist step. The photoresist and unwanted metal (atop the photoresist) are then removed in a solvent bath. PolyMUMPs Post Process HF Release Remove the protective photoresist layer in a solvent bath Immerse chips in a bath of straight 49% HF at room temperature for 2.5 minutes to release the structures Rinse chips in DI water, followed by soaking in isopropyl alcohol and baking in a convection oven 29

30 PolyMUMPs Process Review Add nitride Silicon Substrate 30

31 Add Poly0 (0.5 µm) Silicon Substrate Patterning through 1st level mask (Poly0) using Photolithography Patterned Photoresist Photoresist Silicon Substrate 31

32 Removal of Unwanted Poly0 using Reactive Ion Etching Patterned Photoresist Silicon Substrate 1st Oxide Deposition using LPCVD (2.0 µm) Silicon Substrate 32

33 Patterning through 2nd level mask (Dimple) using Photolithography... and Deep RIE Photoresist (0.75 µm) Silicon Substrate Patterning through 3rd level mask (Anchor) using Photolithography and Deep RIE Photoresist (2.0 µm) Silicon Substrate 33

34 Blanket un-doped polysilicon deposition(poly1) using LPCVD... followed by PSG deposition and annealing (2.0 µm) Silicon Substrate Patterning through 4th level mask (Poly1) using Photolithography... and Deep RIE Photoresist (2.0 µm) Silicon Substrate 34

35 Deposition of 2nd Oxide Layer (0.75 µm) Silicon Substrate Patterning through 5th level mask using photolithography and deep RIE Silicon Substrate (0.75 µm) 35

36 Patterning through 6th level mask using photolithography and deep RIE Silicon Substrate (2.75 µm) Deposition of undoped polysilicon, followed by PSG hardmask layer, then anneal Silicon Substrate (1.5 µm) 36

37 Patterning through 7th level mask using photolithography and deep RIE Silicon Substrate (1.5 µm) Patterning through 8th level mask using photolithography and liftoff, followed by removal of unwanted resist and metal in solvent bath Silicon Substrate (0.5 µm) 37

38 Release of structures using HF Silicon Substrate PolyMUMPs Design Rules Allen Cowen 38

39 MUMPs Design Rules Mask Conventions Nomenclature Minimum Feature/Space Rules Level-Level Rules Poly0 Poly1 & Dimple Poly2 Level-Level Rules (Graphic Form) Helpful Hints Rule Nomenclature Enclose L2 by L1 39

40 Rule Nomenclature L1 to L2 Spacing Rule Nomenclature L2 Cut-Inside L1 40

41 Rule Nomenclature L2 Cut-Outside L1 Mask Conventions Mnemonic Level Name Field Type Purpose POLY0 light pattern ground plane ANCHOR1 dark open holes for POLY1 to nitride or POLY0 connection DIMPLE dark create dimples/bushings for POLY1 POLY1 light pattern POLY1 POLY1_POLY2_VIA dark open holes for POLY1 to POLY2 connection ANCHOR2 dark open holes for POLY2 to nitride or POLY0 connection POLY2 light pattern POLY2 METAL light pattern METAL HOLE0 dark provide holes for POLY0 HOLE1 dark provide release holes for POLY1 HOLE2 dark provide release holes for POLY2 HOLEM dark provide release holes in METAL 41

42 Level Names and Design Rules Mnemonic Level Name CIF Level Name GDS Level # Nominal Line Space Min. Feature Min. Space *POLY0 CPZ *ANCHOR1 COF *DIMPLE COS *POLY1 CPS / *POLY1_POLY2_VIA COT *ANCHOR2 COL *POLY2 CPT / *METAL CCM *HOLE0 CHZ *HOLE1 CHO *HOLE2 CHT *HOLEM CHM POLY0 Rules Rule Rule Letter Figure # Min. Value (µm) POLY0 space to ANCHOR1 A POLY0 enclose ANCHOR1 B POLY0 enclose POLY1 C POLY0 enclose POLY2 D POLY0 enclose ANCHOR2 E POLY0 space to ANCHOR2 F

43 POLY1 Rules Rule Rule Letter Figure # Min. Value (µm) POLY1 enclose ANCHOR1 G POLY1 enclose DIMPLE N POLY1 enclose POLY1_POLY2_VIA H 2.9, POLY1 enclose POLY2 O POLY1 space to ANCHOR2 K *Lateral etch holes space in POLY1 R 2.15 =30 (max. value) POLY2 Rules Rule Rule Letter Figure # Min. Value (µm) POLY2 enclose ANCHOR2 J 2.7, POLY2 enclose POLY1_POLY2_VIA L POLY2 cut-in POLY1 P POLY2 cut-out POLY1 Q POLY2 enclose METAL M POLY2 space to POLY1 I HOLE2 enclose HOLE1 T HOLEM enclose HOLE2 U *Lateral etch holes space in POLY2 S 2.15 =30 (max. value) 43

44 Fig. 2.5 A: POLY0 space to ANCHOR1--4.0um The necessary separation between POLY0 and ANCHOR1 hole to ensure that POLY0 is not exposed. B: POLY0 enclose ANCHOR um. The distance necessary between the edge of POLY0 and an ANCHOR1 hole to ensure the hole does not extend beyond the edge of POLY0. Fig. 2.6 C: POLY0 enclose POLY um The amount POLY0 must extend beyond POLY1 to ensure that POLY0 is an effective ground plane for POLY1 structures. G: POLY1 enclose ANCHOR um. The amount that POLY1 must extend beyond the edge of an ANCHOR1 hole to ensure complete coverage of the hole. 44

45 Fig. 2.7 D: POLY0 enclose POLY2--5.0um The amount POLY0 must extend beyond the edge of a POLY2 structure to ensure that POLY0 is an effective ground plane. J: POLY2 enclose ANCHOR um. The amount POLY2 must extend beyond an ANCHOR2 hole to ensure complete coverage of the hole. Proper Enclosure of Layers Poly2 Poly1 Metal Poly0 45

46 Violation of Enclosure Rules stringer stringer thinned or breached nitride Poly1 Stringers Poly2 P1 Stringer 46

47 Fig. 2.8 E: POLY0 enclose ANCHOR2--5.0um The amount POLY0 must extend past the edge of an ANCHOR2 hole to ensure the hole is over POLY0. F: POLY0 space to ANCHOR2--5.0um The amount of space between an ANCHOR2 hole and POLY0 necessary to prevent subsequent shorting between POLY0 and POLY2. 47

48 Fig. 2.9 H: POLY1 enclose POLY1_POLY2_VIA-4.0um The distance between the POLY1_POLY2_VIA hole and the edge of POLY1 necessary to ensure the via hole is entirely over POLY1. L:POLY2 enclose POLY1_POLY2_VIA--4.0um The amount POLY2 must extend beyond the POLY1_POLY2_VIA hole to ensure complete coverage of the hole. Fig J:POLY2 enclose ANCHOR2--5.0um The amount POLY2 must extend beyond an ANCHOR2 hole to ensure complete coverage of the hole. I:POLY2 space to POLY1--3.0um The space required between POLY1 and POLY2 structures to ensure that the features are separate (no overlap). 48

49 Fig K: POLY1 space to ANCHOR2--3.0um The space between a POLY1 structure and an ANCHOR2 hole necessary to avoid subsequent POLY1-POLY 2 contact. H: POLY1 enclose POLY1_POLY2_VIA--4.0um The distance between the POLY1_POLY2_VIA hole and the edge of POLY1 necessary to ensure the via hole is entirely over POLY1. Fig M: POLY2 enclose METAL--3.0um The distance between the edge of METAL and a POLY2 structure necessary to ensure the entire metal area is on POLY2. 49

50 Fig N: POLY1 enclose DIMPLE--4.0um The amount POLY1 must extend beyond the edge of DIMPLE to ensure the DIMPLE is completely covered by POLY1. Fig P: POLY2 cut-in POLY1--5.0um The minimum amount POLY2 must extend over a POLY1 structure to ensure overlap. O: POLY1 enclose POLY2--4.0um The minimum distance from the edge of POLY1 to POLY2 necessary to ensure the POLY2 does not overlap the POLY1 edge. Q: POLY2 cut-out POLY1--4.0um The minimum distance POLY2 must extend beyond the POLY1 edge to ensure complete edge overlap. 50

51 Fig R: Etch hole separation in POLY1: 30um The maximum separation distance between POLY1 etch holes necessary to ensure subsequent release of POLY1 structures. S: Etch hole separation in POLY2: 30um The maximum separation distance between POLY2 etch holes necessary to ensure subsequent release of POLY2 structures. Fig T: HOLE2 enclose HOLE1--2.0um The necessary border of HOLE2 around HOLE1 to ensure good release results. U; HOLEM enclose HOLE2--2.0um The necessary border of HOLEM around HOLE2 to ensure good release results. 51

52 Stacked Poly nitride oxide poly1 poly2 resist 52

53 Micromotor fabricated using Poly1/Poly2 stack P1/P2 interface Stacked Poly Error Patterned Poly 1 Pooled PR Residual Poly 2 53

54 Words of Advice When drawing a level in layout, ALWAYS draw (digitize) the feature that you want represented on the wafer If you want a poly 1 beam, draw a polygon Draw a poly zero polygon where you want a poly zero electrode If you want a hole, draw a solid polygon to represent the hole A dimple A poly 1 or poly 2 line ANCHOR1+ POLY1_POLY2_VIA vs. ANCHOR2 One of the most common layout errors is the use of ANCHOR1 + POLY1_POLY2_VIA instead of ANCHOR2 ANCHOR1 + POLY1_POLY2_VIA not equal to ANCHOR2 ANCHOR1 removes the oxide and allows poly 1 to contact substrate. If POLY1 is not drawn over the hole, the polysilicon will be removed in the RIE etch and the substrate is exposed to the polysilicon etch. resulting in removal of the nitride layer or etching into the substrate. ANCHOR2 was created to allow connection of poly 2 with the substrate in one mask and etch step When ANCHOR2 is used, the substrate is protected by oxide during the polysilicon etch. There is also no misalignment between the hole in the first and second oxides. 54

55 Breaching the Nitride Layer ANCHOR1 POLY1 P1_P2_VIA or ANCHOR2 That s All Folks! 55

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