FABRICATION of MOSFETs

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1 FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the regions -surrounding the nmos and pmos active regions. -creation of n+ and p+ regions -final metallization & interconnects.

2 CMOS Process PMOS transistors created in an n-well Typically substrate has lower doping on the surface

3 Fabrication Patterning of SiO 2 Grow SiO 2 on Si by exposing to O 2 high temperature accelerates this process Cover surface with photoresist (PR) Sensitive to UV light (wavelength determines feature size) Positive PR becomes soluble after exposure Negative PR becomes insoluble after exposure

4 Fabrication Patterning of SiO 2 PR removed with a solvent SiO 2 removed by etching (HF) Remaining PR removed with another solvent

5 Summary The result of a single lithographic patterning sequence on silicon dioxide, without showing the intermediate steps. unpatterned structure (top) patterned structure (bottom)

6 Fabrication of nmos Transistor Thick field oxide grown Field oxide etched to create area for transistor Gate oxide (high quality) grown

7 Fabrication of NMOS Transistor Polysilicon deposited (doped to reduce R) Polysilicon etched to form gate Gate oxide etched from source and drain Self-aligned process because source/drain aligned by gate Si doped with donors to create n+ regions

8 NMOS Transistor Fabrication Insulating SiO 2 grown to cover surface/gate Source/Drain regions opened Aluminum evaporated to cover surface Aluminum etched to form metal1 interconnects

9 Metallization

10 Device Isolation Techniques To prevent unwanted conduction To avoid creation of inversion layers outside channel regions To reduce leakage currents devices are made into Active areas Surrounded by field oxide (thick oxide barrier)

11 CMOS n-well process P-type substrate n-well region for PMOS thin gate oxide is grown on top of the active regions thick field oxide is grown in the areas surrounding the transistor active regions gate oxide thickness and quality affect the operational characteristics of the MOS transistor and reliability.

12 polysilicon layer deposited by hemical vapor eposition (CVD) patterned by tching. polysilicon lines ill function as the ate of MOS act as selfligned masks for ource and drain

13 Masks n+ and p+ regions implanted in its locations ohmic contacts to substrate and to n-well Contacts to Silicon needs to Be through heavily doped regions To avoid them as junctions

14 Metal (aluminum) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is nonplanar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability

15 Complete

16 mask sequence applied to create desired structures

17 Inverter Fabrication Inverter Logic symbol CMOS inverter circuit CMOS inverter layout (top view of lithographic masks)

18 Inverter layout GND In V DD A A Out (a) Layout A A p-substrate n Field Oxide n + (b) Cross-Section along A-A p +

19 Inverter Fabrication N-wells created Thick field oxide grown surrounding active regions Thin gate oxide grown over active regions

20 Inverter Fabrication Polysilicon deposited Chemical vapor deposition Dry plasma etch

21 Inverter Fabrication N+ and P+ regions created using two masks Source/Drain regions Substrate contacts

22 Inverter Fabrication Insulating SiO 2 deposited using CVD Source/Drain/Substrate contacts exposed

23 Inverter Fabrication Metal (Al) deposited using evaporation Metal patterned by etching

24 Layout Design Rules specify minimum allowable widths for physical objects e.g. metal and polysilicon interconnects or diffusion areas. For the line not to break minimum feature dimensions. To avoid open circuit minimum allowable separations between two such features. To avoid unwanted short circuit main objective To increase possibility of successful product

25 Design rules Micron rules Effitient Layout Non-Scalable, non-transfareble to other technology Lambda (λ) rules Scalled to any technology Ineffetient layout: depends on worst case can make design bigger than needed

26 Lambda (λ)( Is the integer fraction half the minimum fabrication feature size of technology. 1µm technology λ = 0.5 µm Assume W=3 λ and L= 2λ λ = 0.5 µm W=1.5 µm & L =1 µm λ= 0.3 µm W=.9 µm & L =.6 µm Even if technology can give 0.5 µm, L = 0.6 µm because of λ rules

27 Lambda (λ)( ) Rules R1 Minimum active area width 3 λ R2 Minimum active area spacing 3 λ R3 Minimum poly width 2 λ R4 Minimum poly spacing 2 λ R5 Minimum gate extension of poly over active 2 λ R6 Minimum poly-active edge spacing 1 λ (poly outside active area) R7 Minimum poly-active edge spacing 3 λ (poly inside active area) R8 Minimum metal width 3 λ R9 Minimum metal spacing 3 λ R10 Poly contact size 2 λ R11 Minimum poly contact spacing 2 λ R12 Minimum poly contact to poly edge spacing 1 λ R13 Minimum poly contact to metal edge spacing 1 λ R14 Minimum poly contact to active edge spacing 3 λ R15 Active contact size 2 λ R16 Minimum active contact spacing 2 λ (on the same active region) R17 Minimum active contact to active edge spacing 1 λ R18 Minimum active contact to metal edge spacing 1 λ R19 Minimum active contact to poly edge spacing 3 λ R20 Minimum active contact spacing 6 λ (on different active regions)

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32 Stick diagrams showing various CMOS inverter layout options

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