Introduction to Microeletromechanical Systems (MEMS) Lecture 5 Topics. JDS Uniphase MUMPs

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1 Introduction to Microeletromechanical Systems (MEMS) Lecture 5 Topics JDS Uniphase MUMPS Foundry Process and Devices Foundry Process Sequence Design Rules and Process Interactions Examples CMOS for MEMS CMOS Foundry Processes NMOS, PMOS and CMOS MOSIS Orbit 2.0 µm MEMS and CMOS Integration CMOS MEMS Devices High-Aspect Ratio MEMS Structures JDS Uniphase MUMPs Multi User MEMS Process Surface micromachining (originating from Berkeley): 2 released polysilicon layers 2 PSG (phosphosilicate glass) sacrificial layers 1 metal layer 7 layers total: Nitride - Poly0 - Oxide1 - Poly1 - Oxide2 - Poly2 - Metal 8 masks: POLY0 - DIMPLES - ANCHOR1 - POLY1 - POLY1_POLY2_VIA - ANCHOR2 - POLY2 - METAL See MUMPs Design Handbook (available online at:

2 MUMPs MUMPs Design Handbook Chapter 1 MUMPs Design Rules MUMPs Design Handbook Chapter 2 (selected pages)

3 MUMPs Process Cross Sectional View Of The MUMPs Process (not to scale) MUMPs Examples

4 MUMPs Process Si wafers, 1-2Ω resistivity 600nm LPCVD Si 3 N 4 500nm LPCVD polysilicon (poly-0) Lithography POLY0 (HOLE0) and RIE poly-0 2.0µm LPCVD phosphosilicate glass (oxide-1) and 1050 C anneal Lithography DIMPLES and RIE PSG (750nm) Lithography ANCHOR1 and RIE PSG 2.0µm LPCVD polysilicon (poly-1) Lithography POLY1 (HOLE1) and RIE poly µm LPCVD PSG (oxide-2) and 1050 C anneal Lithography POLY2-POLY1-VIA and RIE PSG (oxide-2) Lithography ANCHOR2 and RIE PSG (oxide-2 and oxide-1) MUMPs Process 1.5µm LPCVD polysilicon (poly-2) Lithography POLY2 (HOLE2) and RIE poly-2 0.5µm Cr/Au evaporation (metal) Lithography METAL (HOLEM) and liftoff Dicing and sorting Optional: min 49% HF sacrificial oxide etch at room temperature Optional: CO 2 critical point drying Shipping

5 MUMPs Devices Examples: Micro optics bench [Wu et al. 1996] Heart cell force sensor [Lin et al. 1995] Linear and rotary impact drives [Sinclair 1999] MUMPs Mask Conventions Definitions: Light field mask: features are defined in CAD layout and appear dark, background appears light Dark field mask: holes are defined in CAD layout and appear light, background appears dark MUMPs Rule: Draw patterns in polysilicon and metal (POLYx and METAL are light field) Draw holes in sacrificial layers (ANCHORx, DIMPLE, VIA, and HOLEx are dark field)

6 Features And Holes Concept CAD draw feature or hole Mask light field or dark field Resist positive or negative Image reversal no or yes Process pattern transfer or lift-off Structure Exercise: MUMPs Layout Examples What happens if we draw no features at all? What happens if we draw features on every layer (except holes)? (POLY0, DIMPLE, ANCHOR1, POLY1, POLY2_POLY1_VIA, ANCHOR2, POLY2, METAL) What happens if we draw ANCHOR1, POLY1_POLY2_VIA, and POLY2? What happens if we draw continuous sheets of POLY1 and POLY1_POLY2_VIA, and a specific POLY2 structure?

7 Hinges For 3D MEMS MEMS fabricated with conventional micromachining processes are essentially 2D (or 2½D ) Access to 3rd dimension with fold-up structures [Pister et al.1992] Are multi-link hinged structures possible in MUMPs? Figures: Kovacs 1998 Assembly/Deployment Of MEMS One-Time Deployment Of 3D Structures Manual assembly (tweezer, probe station, microscope) Agitation in fluid [Pister et al. 1992] Deployment actuators (Sandia) Assembly mechanism [Hui et al. 2000] Self-assembly inspired by chemistry and biology Sandia National Labs Hui et al. MEMS 2000

8 MEMS Pop-Up Structures A) Unassembled pop-up cornercube reflector. B) CCR after assembly. The assembly was accomplished in a single flipping step. C) A similar CCR structure in partially assembled state. Designed in Sandia SUMMiT 4-level process by Elliot Hui, UC Berkeley Other Processes And Foundries CMOS Foundry Processes NMOS, PMOS and CMOS MOSIS Orbit 2.0 µm MEMS in CMOS CMOS MEMS Devices Bridges and cantilevers Hinges Multi-axis accelerometer

9 CMOS MEMS CMOS (complementary metal oxide semiconductor): the standard technology to build integrated circuits (ICs) Reasons for using CMOS for MEMS: Widely available foundry processes Well established and characterized Get integrated electronics for free (compare with MEMS pre or post processing) NMOS n-channel Metal Oxide Semiconductor Lilienfield, 1927, first transistor switch; US Patents 1,745,175 and 1,900,018. Bardeen, Brattain and Shockley, 1947, first bipolar transistor; Nobel Prize in Physics, n +5V Positive charge on gate creates n-type channel in p-doped substrate (Field Effect Transistor, FET) n p Comparison: capacitor G S D Switch 0V 5V

10 NMOS Fabrication p Grow 4000Å oxide on p-type silicon substrate As p p Pattern and etch oxide, then ion implant As to form n region Grow thin oxide (200Å), pattern and etch oxide to form contact Deposit 5000Å aluminum, pattern and etch aluminum Si SiO 2 n-si Al p NMOS capacitor NMOS Components Source Gate Drain p NMOS transistor Si SiO 2 n-si Al PSG

11 PMOS p-channel Metal Oxide Semiconductor p p V n Negative charge on gate creates p-type channel in n-doped substrate S G D Switch Comparison: capacitor 0V 5V CMOS Complementary Metal Oxide Semiconductor NMOS PMOS +5V Uses both NMOS and PMOS transistors Minimize power: high current only briefly during switching V out I PMOS NMOS V in +5V V in V out

12 CMOS V out Inverter NMOS PMOS +5V V out V in V in I PMOS NMOS +5V V out V in CMOS Inverter V in V out +5V n n p p p-well n-substrate Fabrication similar to PMOS, but we need additional pwell (= p-tub ) in n-type substrate (or vice versa) Doping of p-well overcompensates n-type doping of substrate Twin well process is also possible

13 CMOS Fabrication (simplified) / NWEL ion implant P Grow 100Å pad oxide Deposit 1000Å nitride / ACTV Grow 0.6 µm field oxide Strip nitride / pad oxide Grow 400Å gate oxide Deposit 0.4 µm n+poly / POLY / PSEL ion implant B, anneal (self-aligning) note: anneal not possible with Al pad / NSEL ion implant P, anneal CMOS Fabrication (simplified) Deposit 0.5µm LPCVD oxide, reflow / CONT Sputter Al + 2% Si / MET1 Ground V out +5V Deposit 0.6µm LPCVD oxide / VIA1 Sputter Al + 2% Si / MET2 Repeat oxide / Al as desired Deposit overglass 1µm / OG protective layer / holes for bonding pads

14 Mask Layers: CMOS Design NWEL defines n-well in p-type substrate ACTV active region (substrate exposed) POLY polysilicon (gates) PSEL p-type areas (in n-well) NSEL n-type areas CONT CMOS contacts MET1 metal layer 1 VIA1 via metal 1 - metal 2 MET2 metal layer 2 OG bonding pads CAD Convention: Draw conductors (Al, poly) CMOS CAD Example 1: Don t draw anything End up with Si, field oxide, Draw holes in dielectrics oxide 1, oxide 2, overglass (oxide, nitride, OG) Example 2: Draw all contacts (ACTV, CONT, VIA, OG) End up with bare Si (metal etch chews into Si) unpredictable

15 CMOS Example MET1 MET2 MET1, MET2 PIT (ACTV, CONT, VIA, OG) Design Rules (2µm Orbit) LayerLine / Space NWEL 10 / 9 ACTV 3 / 3 POLY 2 / 2 MET1 3 /3 MET2 3 / 4 OG 20 / 20 PIT 20 / 20 CONT - VIA (MET1 - POLY, MET1 - ACTV, MET1- MET2) 2 x 2 (2 µm space) Conductor Overlap 2 µm tolerance

16 2 µm Orbit Specifications 2 µm Orbit Specifications

17 CMOS Al Microhinge Hoffman, Warneke, Kruglick, Weigold and Pister (MEMS 1995) use CMOS field oxide as sacrificial layer BOE release etch Al provides mechanical and electrical connection for hinged structures Si SiO 2 Poly Al CMOS Al Microhinge Hoffman, Warneke, Kruglick, Weigold and Pister (MEMS 1995) XeF 2 bulk isotropic Si release etch Can vary stiffness of hinges and released structures Si SiO 2 Poly Al

18 CMOS Microbridge Parameswaran, Baltes, Ristic, Dhaded and Robinson (Sensors and Actuators, 19, 1989) use CMOS field oxide as sacrificial layer Also: - Expose silicon substrate - Etch stop with heavily doped source/drain Si Si SiO 2 Poly Al Review Of XeF 2 Isotropic Silicon Etch Post-processing for standard CMOS Suspended and 3D structures Fold-up structures with conducting Al hinges Tahhan et al (UC Berkeley) Warneke et al (UCLA) Storment et al (Stanford)

19 3-Axis CMOS Accelerometer Regular 2 µm CMOS foundry process Single maskless post-processing step Kruglick, Warneke and Pister, MEMS, Accelerometer With CMOS/DRIE X. Zhu,D. W. Greve, G. K. Fedder, Characterization of Silicon Isotropic Etch by Inductively Coupled Plasma Etch in Post-CMOS Processing, IEEE MEMS 2000, Myazaki, Japan.

20 Fundamental MEMS Processes And Devices High Aspect-Ratio Micro Structures (HARMST) LIGA SU-8 The LIGA Process LIGA stands for Lithographie, Galvanoformung, Abformung (german) - Lithography, Electroplating, Molding Invented in the late 70 s at the Nuclear Research Center, Karlsruhe, Germany Very high-aspect ratio microstructures achieved with X-ray lithography Figure: Institute for Microstructure Technology (FZK), Karlsuhe, Germany Figure: G. Kovacs 1996

21 LIGA Process Sequence Figure: W. Menz, J. Mohr and O. Paul, 2001, p LIGA Process (a) Plastic (usually PMMA, polymethyl methacrylate) on conductive substrate; several 100 µm thick. Exposure with very parallel X-rays (λ = nm) and development (b) Electroplating and removal of remaining PMMA (Cu, Ni, Au, ) (c) Injection molding in metal master (mass production) (d) Further processing (additional electroplating, )

22 LIGA Mask: LIGA Mask Making Absorber (for X-rays): Au (> 10 µm) Carrier foil (transmission of X-rays, structural support of mask features): low absorbance and high resistance to X-rays required: Be, C, S, Frame (typical: 25 mm x 65 mm) LIGA Mask Making Intermediate Mask Final Mask Intermediate mask required to make final mask Figure: W. Menz, J. Mohr, O. Paul, 2001, p. 294.

23 X-Ray Lithography Issues Source: synchrotron Resist sensitive to X-rays Irradiation breaks up polymer chains Developer / solvent for breakup products Figure: W. Menz, J. Mohr and O. Paul 2001, p Electroplating In LIGA PMMA structures made in LIGA can be the end product Or, they can be a template for an electroplating process That process, in turn, can produce the master for a molding process Those molds, in turn, can be used in other production processes Figure: W. Menz, J. Mohr and O. Paul 2001, p. 320.

24 Mold Template Fabrication Electroplating over PMMA structures Continues beyond height of PMMA structures to form continuous metal plate Polishing Figure: W. Menz, J. Mohr and O. Paul 2001, p Advantages Of LIGA Very high-aspect ratios Smooth sidewalls (compare to DRIE) Mass production by molding Disadvantages: Synchrotron required Material selection limited Complex processing steps (see, e.g., mask making) High start-up costs Figure: W. Menz, J. Mohr and O. Paul 2001, p. 310.

25 Applications Electrostatic comb drive Microturbines and flow sensors Figures: W. Menz, J. Mohr and O. Paul, 2001, p Applications Electromagnetic Actuator

26 LIGA Lithographie, Galvanoformung, Abformung (German: Lithography, Electroplating, Molding) Very high-aspect ratio micro molds Figure: G. Kovacs 1996 Alternatives To LIGA DRIE (deep reactive ion etching in Si): now widely used in academia and industry sidewalls not smooth ( scallops ) SU-8 ( poor man s LIGA )

27 SU-8 Thick Photoresists Negative UV Photoresist Up to 1200µm thickness (> 300 µm single spin) Aspect ratios up to 20:1 Processing with regular lithography equipment Features: Fast prototyping Durable structural material (epoxy) Adhesion to substrate materials? High stresses in SU-8 layers Low cost SU-8 Thick Photoresist Composition: Organic solvent GBL (gamma-butyloracton), determines viscosity and, thus, film thickness Epoxy resin (EPON resin SU-8) Photoinitiator Exposed SU-8 polymerizes and forms very durable structures Chemical amplification: chain reaction during exposure helps formation of vertical sidewalls

28 Thick-Film Photoresists Recently, results similar to LIGA have been achieved with SU-8, a negative photoresist for UV optical lithography Single and multi level structures: low cost molded watch gears (EPFL Switzerland 1997) X-ray detector (Brookhaven National Labs 1998)