EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

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1 EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

2 Review from Last Time Etching Dry etch (anisotropic) SiO 2 Photoresist p - Silicon Desired Physical Features Dry Etch can provide very well-defined and nearly vertical edges (relative to photoresist paterning)

3 Review from Last Time Etching Undercutting (wet etch) Photoresist SiO 2 p - Silicon Isotropic Feature Degradation Desired Edges of SiO 2 from Mask Edge Movement Due to Over Etch, Over Exposure, or Over- Development

4 Review from Last Time Etching (limited by photolitghographic process) SiO 2 Dry etch (anisotropic) Photoresist p - Silicon Dry etch (anisotropic) Consider neg photoresist Over Exposed Correctly Developed Over Developed Under Developed Under Exposed Correctly Developed Over Developed Under Developed

5 Review from Last Time Diffusion Implant p - Silicon p- Silicon Lateral Diffusion Before Diffusion p - Silicon p- Silicon After Diffusion

6 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Ion Implantation Etching Diffusion Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization

7 Oxidation SiO 2 is widely used as an insulator Excellent insulator properties Used for gate dielectric Gate oxide layers very thin Used to separate devices by raising threshold voltage termed field oxide field oxide layers very thick Methods of Oxidation Thermal Growth (LOCOS) Consumes host silicon x units of SiO 2 consumes.47x units of Si Undercutting of photoresist Compromises planar surface for thick layers Excellent quality Chemical Vapor Deposition Needed to put SiO 2 on materials other than Si

8 Oxidation Photoresist SiO 2 X 0.47 X p - Silicon Patterned Edges Thermally Grown SiO 2 - desired growth

9 Oxidation Bird s Beaking Photoresist SiO 2 p - Silicon Patterned Edges Thermally Grown SiO 2 - actual growth

10 Nonplanar Surface Oxidation p - Silicon Patterned Edges Thermally Grown SiO 2 - actual growth

11 Silicon Nitride Oxidation Photoresist Pad Oxide p - Silicon Shallow Trench Isolation (STI)

12 Oxidation Silicon Nitride Etched Shallow Trench Pad Oxide p - Silicon Shallow Trench Isolation (STI)

13 Silicon Nitride Oxidation CVD SiO 2 Pad Oxide p - Silicon Shallow Trench Isolation (STI)

14 Oxidation Planarity Improved Planarization Target p - Silicon Shallow Trench Isolation (STI)

15 Oxidation After Planarization CVD SiO 2 p - Silicon Shallow Trench Isolation (STI)

16 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Planarization Contacts, Interconnect and Metalization

17 Epitaxy Single Crystaline Extension of Substrate Crystal Commonly used in bipolar processes CVD techniques Impurities often added during growth Grows slowly to allow alignmnt with substrate

18 Epitaxy Epitaxial Layer p - Silicon epi can be uniformly doped or graded Original Silicon Surface Question: Why can t a diffusion be used to create the same effect as an epi layer?

19 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Planarization Contacts, Interconnect and Metalization

20 Polysilicon Elemental contents identical to that of single crystaline silicon Electrical properties much different If doped heavily makes good conductor If doped moderately makes good resistor Widely used for gates of MOS devices Widely used to form resistors Grows fast over non-crystaline surface Patterned with Photoresist/Etch process Silicide often used in regions where resistance must be small Refractory metal used to form silicide Designer must indicate where silicide is applied (or blocked)

21 Polysilicon Polysilicon Single-Crystaline Silicon

22 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Planarization Contacts, Interconnect and Metalization

23 Planarization Planarization used to keep surface planar during subsequent processing steps Important for creating good quality layers in subsequent processing steps Mechanically planarized

24 IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Planarization Contacts, Interconnect and Metalization

25 Contacts, Interconnect and Metalization Contacts usually of a fixed size All etches reach bottom at about the same time Multiple contacts widely used Contacts not allowed to Poly on thin oxide in most processes Dog-bone often needed for minimum-length devices

26 Contacts A A B B Acceptable Contact Unacceptable Contact Vulnerable to pin holes (usually all contacts are same size)

27 Contacts B B Acceptable Contact

28 Contacts 2λ 2λ 1.5λ 1.5λ 2λ Dog Bone Contact Design Rule Violation

29 Contacts Common Circuit Connection Standard Interconnection Buried Contact Can save area but not allowed in many processes

30 Metalization Aluminum widely used for interconnect Copper finding some applications Must not exceed maximum current density around 1ma/u Ohmic Drop must be managed Parasitic Capacitances must be managed Interconnects from high to low level metals require connections to each level of metal Stacked vias permissible in some processes

31 Metalization Aluminum Aluminum is usually deposited uniformly over entire surface and etched to remove unwanted aluminum Mask is used to define area in photoresist where aluminum is to be removed Copper Plasma etches not effective at removing copper because of absence of volatile copper compounds Barrier metal layers needed to isolate silicon from migration of copper atoms Damascene or Dual-Damascene processes used to pattern copper

32 Patterning of Aluminum Contact Opening from Mask Photoresist

33 Patterning of Aluminum Contact Opening after SiO 2 etch Photoresist

34 Patterning of Aluminum Contact Opening after SiO 2 etch Photoresist

35 Patterning of Aluminum Metal Applied to Entire Surface

36 Patterning of Aluminum Photoresist Patterned with Metal Mask

37 Patterning of Aluminum Aluminum After Metal Etch (photoresist still showing)

38 Copper Interconnects Limitations of Aluminum Interconnects Electromigration Conductivity not real high Relevant Key Properties of Copper Reduced electromigration problems at given current level Better conductivity Challenges of Copper Interconnects Absence of volatile copper compounds (does not etch) Copper diffuses into surrounding materials (barrier metal required)

39 Copper Interconnects Practical methods of realizing copper interconnects took many years to develop Copper interconnects widely used in some processes today

40 Damascene Process Patterning of Copper Contact Opening after SiO 2 etch Photoresist

41 Damascene Process Patterning of Copper Tungsten (W) CMP Target W has excellent conformality when formed from WF6

42 Chemical-Mechanical Planarization (CMP) Polishing Pad and Wafer Rotate in non-concentric pattern to thin, polish, and planarize surface Abrasive/Chemical polishing Depth and planarity are critical Acknowledgement:

43 Patterning of Copper Damascene Process After first CMP Step CMP Target W-plug

44 Damascene Process Patterning of Copper After first CMP Step Oxidation

45 Damascene Process Patterning of Copper Photoresist Patterned with Metal Mask Defines Trench

46 Patterning of Copper Damascene Process Shallow Trench after Etch W-plug

47 Damascene Process Patterning of Copper Barrier Metal (Barrier metal added before copper to contain the copper atoms)

48 Damascene Process Patterning of Copper W-plug Copper Deposition

49 Patterning of Copper Damascene Process W-plug CMP Target Copper Deposition Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)

50 Patterning of Copper Damascene Process After Second CMP Step W-plug Copper CMP Target

51 Dual-Damascene Process Patterning of Copper Shallow Trench Defined in PR with Metal Mask Photoresist

52 Dual-Damascene Process Patterning of Copper Shallow Trench After Etch Photoresist

53 Dual-Damascene Process Patterning of Copper Via Defined in PR with Via Mask Photoresist

54 Dual-Damascene Process Patterning of Copper Via Etch Defines Contact Region Photoresist (Barrier Metal added before copper but not shown)

55 Dual-Damascene Process Patterning of Copper Copper Deposited on Surface Copper is deposited or electroplated (Barrier Metal Used for Electroplating Seed)

56 Dual-Damascene Process Patterning of Copper Copper Deposited on Surface CMP Target

57 Dual-Damascene Process Patterning of Copper Copper Via Copper Interconnect CMP Target

58 Patterning of Copper Both Damascene Processes Realize Same Structure Damascene Process Two Dielectric Deposition Steps Two CMP Steps Two Metal Deposition Steps Two Dielectric Etches W-Plug Dual-Damascene Process One Dielectric Deposition Steps One CMP Steps One Metal Deposition Steps Two Dielectric Etches Via formed with metal step

59 Multiple Level Interconnects 3-rd level metal connection to n-active without stacked vias

60 Multiple Level Interconnects 3-rd level metal connection to n-active with stacked vias

61 End of Lecture 9

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