EE 143 CMOS Process Flow
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1 EE 143 CMOS rocess Flow CT 84 D D G Sub G Sub S S G D S G D S MOS Substrate Well - MOS Substrate
2 EE 143 CMOS rocess Flow CT 85 hotoresist Si 3 4 SiO 2 Substrate selection: moderately high resistivity, (100) orientation, type. Si, (100), Type, 5-50 žcm Wafer cleaning, thermal oxidation ( 40 nm), nitride LCVD deposition ( 80 nm), photoresist spinning and baking ( µm). Mask #1 patterns the active areas. The nitride is dry etched. Field oxide is grown using a LOCOS process. Typically C in H 2 O grows 0.5 µm. Boron Implant Mask #2 blocks a B+ implant to form the wells for the MOS devices. Typically cm KeV.
3 EE 143 CMOS rocess Flow CT 86 hosphorus Implant Implant Mask #3 blocks a + implant to form the wells for the MOS devices. Typically cm 300+ KeV. Well A high temperature drive-in produces the final well depths and repairs implant damage. Typically C C or equivalent Dt. Boron Well Mask #4 is used to mask the MOS devices. A V TH adjust implant is done on the MOS devices, typically a 1-5 x cm -2 B KeV. Arsenic Well Mask #5 is used to mask the MOS devices. A V TH adjust implant is done on the MOS devices, typically 1-5 x cm -2 As KeV.
4 EE 143 CMOS rocess Flow CT 87 Well The thin oxide over the active regions is stripped and a new gate oxide grown, typically 3-5 nm, which could be grown in C in O2. Well olysilicon is deposited by LCVD ( 0.5 µm). An unmasked + or As+ implant dopes the poly (typically 5 x cm -2 ). Well Mask #6 is used to protect the MOS gates. The poly is plasma etched using an anisotropic etch. hosphorus - Implant Well Mask #7 protects the MOS devices. A + implant forms the LDD regions in the MOS devices (typically 5 x cm 50 KeV).
5 EE 143 CMOS rocess Flow CT 88 Boron - Implant - Implant Well Mask #8 protects the MOS devices. A B+ implant forms the LDD regions in the MOS devices (typically 5 x cm 50 KeV). - Implant - Implant Well Conformal layer of SiO2 is deposited (typically 0.5 µm). - Implant - Implant Well Anisotropic etching leaves sidewall spacers along the edges of the poly gates. Arsenic + Implant Well Mask #9 protects the MOS devices, An As+ implant forms the MOS source and drain regions (typically 2-4 x cm 75 KeV).
6 EE 143 CMOS rocess Flow CT 89 Boron + Implant + Implant Well Mask #10 protects the MOS devices, A B+ implant forms the MOS source and drain regions (typically 1-3 x cm 50 KeV) Well A final high temperature anneal drives-in the junctions and repairs implant damage (typically C or 1 min 1000 C) Well An unmasked oxide etch allows contacts to Si and poly regions Well Ti is deposited by sputtering (typically 100 nm).
7 EE 143 CMOS rocess Flow CT Well The Ti is reacted in an 2 ambient, forming TiSi 2 and Ti (typically C) Well Mask #11 is used to etch the Ti, forming local interconnects Well A conformal layer of SiO 2 is deposited by LCVD (typically 1 µm) Well CM is used to planarize the wafer surface.
8 EE 143 CMOS rocess Flow CT Well Mask #12 is used to define the contact holes. The SiO 2 is etched. W Ti Well A thin Ti barrier layer is deposited by sputtering (typically a few tens of nm), followed by W CVD deposition Well CM is used to planarize the wafer surface, completing the damascene process. Al is deposited on the wafer Well by sputtering. Mask #13 is used to pattern the Al and plasma etching is used to etch it.
9 EE 143 CMOS rocess Flow CT Well Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si 3 4 is deposited by ECVD and patterned with Mask #16. Differences from older long-channel CMOS: 1. Very thin lightly doped drain (LDD) and source junctions; very small x j 2. Very thin gate oxide 3. Much higher channel & substrate doping So why these differences? Answer: punchthrough!
10 EE 143 Bulk unchthrough CT 93
11 EE 143 CMOS rocess Flow CT Well Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si 3 4 is deposited by ECVD and patterned with Mask #16. Differences from older long-channel CMOS: 1. Very thin lightly doped drain (LDD) and source junctions; very small x j 2. Very thin gate oxide 3. Much higher channel & substrate doping So why these differences? Answer: punchthrough! Remarks: More advanced technologies also require a thinner gate oxide, for reasons explained above SiO 2 can no longer satisfy, since the gate oxide thicknesses below 1 nm have leakage issues ewest technologies use ALD high-k oxides (e.g., HfO 2 ) More advanced technologies must reduce as much as possible the interconnect capacitance low-k inter-metal dielectrics The use of LOCOS in this process limits it to m channel lengths Any smaller and the LOCOS encroachment it too much lus, the topography makes lithography for smaller channel lengths more difficult
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