CMOS Manufacturing process. Design rule set
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1 CMOS Manufacturing process Circuit design Set of optical masks Fabrication process Circuit designer Design rule set Process engineer All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, second edition, Prentice Halls, 2002
2 Simplified very basic CMOS Process CMOS inverter n-well process 58
3 A Modern CMOS Process CMOS inverter dual-well trench-isolated process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ 59
4 Circuit Under Design V DD V DD M2 M4 V in V out V out2 M1 M3 60
5 61 Its Layout View
6 Silicon ingot Diameter 12 inches (300 mm) Weight 100 Kg
7 Photo-Lithographic Process Oxidation 1000 C optical mask Clean room (class 1-10) process step photoresist removal (ashing) spin, rinse, dry photoresist coating (1um) Typical operations in a single photolithographic cycle (from [Fullman]). stepper exposure acid etch photoresist development Def: Class 1: <1 dust particle per cubic foot In each processing step, an area of the chip is masked out using optical masks, so that the process step is selectively applied to the other regions 63
8
9
10 Example of process stemp: Patterning of SiO2 Si-substrate (a) Silicon base material Si-substrate Photoresist SiO 2 Si-substrate Chemical or plasma etch Hardened resist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (b) After oxidation and deposition of negative photoresist Hardened resist SiO 2 UV-light Patterned optical mask Si-substrate (e) After etching Exposed resist SiO 2 Si-substrate (c) Stepper exposure Si-substrate (f) Final result after removal of resist 66
11 Doping Recurring process steps (1/2) Diffusion(gas with dopant, o C) Ion implantation Lattice damage (displacement of atoms) Annealingstep (1000 o Cfor slow cooling) Deposition(of layers over the complete wafer) Oxidation[silicon oxide] Chemical Vapor Deposition: gas phase + heat (850 o C) [silicon nitride] Chemical deposition (polysilicon: silane(sih 4 ) gas over heated wafer (600 o C) reaction an polysilicon formation Sputtering(for aluminum): evaporation in vacuum chamber
12 Recurring process steps (2/2) Etching (defines 3D patterns on the surface) Wet etching (with acid or basic solutions) e.g. Hydrofluoric acid for silicon oxide Almost isotropic Dry or plasma etching Plasma: mix of nitrogen, chlorine, boron trichloride Strongly anisotropic (steep vertical edges) Planarization (flatten the surface to allow layer deposition) Chemical Mechanical Polishing (CMP) Liquid carrier with a suspended abrasive component
13 Simplified CMOS Process flow Define active areas Etch and fill trenches Implant well regions Active areas: where transistors are Field oxide: insulator between neighboring devices Wells in the active areas Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Gate stack Contact doping Create contact and via windows Deposit and pattern metal layers Metal Interconnects 69
14 CMOS Process Walk-Through p-epi p+ (a) Base material: p+ substrate with p-epi layer p-epi p+ SiN 3 4 SiO 2 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask 70
15 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride n (e) After n-well and V Tp adjust implants p (f) After p-well and V Tn adjust implants 71
16 CMOS Process Walk-Through poly(silicon) (g) After polysilicon deposition and etch n+ p+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. SiO 2 (i) After deposition of SiO 2 insulator and contact hole etch. 72
17 CMOS Process Walk-Through Al (j) After deposition and patterning of first Al layer. Al SiO 2 (k) After deposition of SiO 2 insulator, etching of via s, deposition and patterning of second layer of Al. 73
18 74 Advanced Metallization
19 75 Advanced Metallization
20 CMOS Manufacturing process Circuit design Set of optical masks Fabrication process Circuit designer Design rule set Process engineer All material: Chap. 2 of J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits, second edition, Prentice Halls, 2002
21 Design Rules Minimum line width depend on lithographyand process Micron rules: absolute dimensions for intra-layer and inter-layer layouts 77
22 78 Layers in 0.25 µm CMOS process
23 79 Intra-Layer Design Rules
24 80 Transistor Layout
25 81 Vias and Contacts
26 82 Select Layer
27 CMOS Inverter Layout
28 84 Layout Editor
29 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um. 85
30 Sticks Diagram V DD 3 In 1 Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 86
31 Packaging Requirements Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap 87
32 Bonding Techniques Wire Bonding Substrate Die Pad Lead Frame 88 Gold wires, large inductance
33 Tape-Automated Bonding (TAB) Sprocket hole Film + Pattern Solder Bump Test pads Die Lead frame Substrate (b) Die attachment using solder bumps. (a) Polymer Tape with imprinted wiring pattern. Polymer film 89
34 Flip-Chip Bonding Die Solder bumps Top (where circuit is) Interconnect layers Substrate 90
35 Package-to-Board Interconnect (a) Through-Hole Mounting (b) Surface Mount 91
36 Package Types DIP PLCC PGA 92
37 93 Package Parameters
38 94 Multi-Chip Modules
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