Characteristics of Silicon Carbide Nanowires Synthesized on Porous Body by Carbothermal Reduction

Transcription

1 Jurnal f the Krean Ceramic Sciety Vl. 55, N. 3, pp. 285~289, Cmmunicatin Characteristics f Silicn Carbide Nanwires Synthesized n Prus Bdy by Carbthermal Reductin Jung-Hun Kim and Sung-Churl Chi Divisin f Materials Science and Engineering, Hanyang University, Seul 04763, Krea (Received February 13, 2018; Revised April 16, May 3, 2018; Accepted May 4, 2018) ABSTRACT We synthesized silicn carbide (β-sic) nanwires with nan-scale diameter ( nm) and micr-scale length ( µm) n a prus bdy using lw-grade silica and carbn black pwder by carbthermal reductin at C. The SiC nanwires were frmed by vapr-liquid-slid depsitin with self-evaprated Fe catalysts in lw-grade silica. We investigated the characteristics f the SiC nanwires, which were grwn n a prus bdy with Ar flwing in a vacuum furnace. Their structural, ptical, and electrical prperties were analyzed with X-ray diffractin (XRD), transmissin electrn micrscpy (TEM), and selective area electrn diffractin (SAED). We btained high-quality SiC single crystalline nanwire withut stacking faults that may have uses in industrial applicatins. Key wrds : SiC, One-dimensinal nanstructure, Prus bdy, Stacking fault I 1. Intrductin n the recent past, ne-dimensinal (1D) nanstructures with nanmeter diameters, such as nanwires, nanrds, and nantubes, have attracted increased interest due t their ptical, electrical, and mechanical prperties. Ptential applicatins range frm prbe micrscpy tips t intercnnectins in nandevices. Therefre, current researchers have fcused n develping industrial methds and imprving available applicatins fr large-scale synthesis f highquality crystalline nanstructures. 1-3) Silicn carbide (SiC) is an imprtant wide band gap semicnductr with superir prperties, such as high breakdwn field strength, high thermal cnductivity, high saturatin drift velcity, and excellent physical and chemical stability. 4) The use f mdern SiC technlgies has led t a rapid imprvement in the material quality f SiC and has made practical SiC devices a reality. Researchers frm different fields have prpsed several appraches, such as carbn-nantube cnfined reactin, chemical vapr depsitin, laser ablatin, arc discharge, sl-gel methds, and carbthermal reductin fr grwth f 1D SiC nanstructures using bttm-up prcesses. 5-9) There exist multiple methds fr grwing 1D SiC whiskers and wires, but cntrlling stacking faults and ther defects during synthesis still remains a challenge. Stacking faults are usually fund in 3C-SiC structures and affect their varius prperties. 10) Se et al. prefrmed studies n varius mrphlgies and stacking fault insertins in SiC whiskers grwn using carbthermal reductin. 11) They Crrespnding authr : Sung-Churl Chi chi0505@hanyang.ac.kr Tel : Fax : successfully cntrlled the mrphlgies and fault angle in SiC whiskers fr use as a reinfrcement in cmpsite materials. In this study, we synthesized β-sic nanwires with diameters in nanscale range n a prus bdy and silicn wafer substrate using lw-grade silica and carbn black pwder via carbthermal reductin at 1400 C. We then investigated their structural characteristics. 2. Experimental Prcedure In carrying ut the carbthermal reductin prcess fr grwth f SiC nanwires, we used a vacuum furnace ( Trr, 2400 C maximum temperature) with inert Ar gas. Lwer grade silica (purity: 97.5%, Samchun Pure Chemical C., Krea) and amrphus carbn black pwder (Purified Carbn Black, < 200 nm, SUPELCO, USA) were chsen as the starting materials as they have the advantage f inducing high reactivity. The starting materials were fabricated using the prus bar-type ( cm 3 ) green bdy mixed with silica and carbn black pwder with 1 : 3 wt% rati. The prus green bdy enabled material surces t be evaprated fr grwth f SiC nanwires in the carbthermal reductin prcess. An Si substrate (wafer with (100) expsed plane) was lcated clse t the prus bdy in rder t cmpare the nanwires grwn n the prus bdy (PBSiC) and thse grwn n the Si wafer (SWSiC). SiC nanwires were grwn at C temperature, min hlding time, and Ar gas flw rate in the 500-2,000 sccm range. Hwever, we chse SiC nanwire samples that were grwn at temperatures belw 1450 C because the Si substrate melted at higher temperatures. Ar gas was intrduced t maintain an inert atmsphere during the heat-up perid. After the furnace was cled t rm 285

2 286 Jurnal f the Krean Ceramic Sciety - Jung-Hun Kim and Sung-Churl Chi Vl. 55, N. 3 temperature, a gray layer n the prus bdy surface and light green layer n the Si wafer surface were bserved. The mrphlgies f PBSiC and SWSiC nanwires were bserved and analyzed using scanning electrn micrscpy (SEM; Tescan Vega TS 5136XM, Czech Republic). X-ray diffractin (XRD; Rigaku-GDX-XRD, Rigaku C., Japan) was used t determine the crystalline phases and measure and cmpare the stacking fault cntent in the nanwires. 10) Stacking faults in individual nanwires were characterized using high-reslutin transmissin electrn micrscpy (HRTEM; Tecnai G2 F30 S-Twin, FEI, USA)) images and selective area electrn diffractin (SAED) patterns. Energy dispersive spectra (EDS) were btained using an HRTEM equipped with an energy-dispersive spectrscpy (EDS) system. 3. Results and Discussin In rder t grw 1D SiC nanwires by carbthermal reductin, we started with a prus bdy cmpsed f silica and carbn black pwder. The verall reactin in the prus bdy between each f the pwders fr prducing SiC is as fllws: Silica(s) + 3C(s) SiC(s) + 2CO(g) (1) Silica(s.l) + C(s) SiO(g) + CO(g) (2) SiO(g) + 2C(s) SiC(s) + CO(g) (3) In fact, Eq. (1) prceeds thrugh tw stages in which silicn mnxide (SiO) gas is frmed as a vapr phase intermediate. The first step cnsists f a slid-slid r slid-liquid type f reactin between carbn and silica, leading t the frmatin f silicn mnxide and carbn mnxide (CO) vapr phases accrding t Eq. (2). Eq. (3) shws the secnd step, where silicn mnxide subsequently reacts with carbn t frm SiC. Silicn mnxide btained frm Eq. (2) reacts with carbn t yield SiC nuclei hetergeneusly n the surface f carbn, which is the cmmnly accepted mechanism f bulk SiC frmatin. 12) Hwever, the vapr-liquid-slid (VLS) grwth mechanism is well-knwn. Silicncarrying and carbn-carrying liquid drplets are frmed by melting metallic catalysts that were added intentinally. The evaprated silicn and carbn atms diffuse acrss the drplet and depsit t frm SiC nanwires. 13) Figure 1 shws a schematic diagram fr the grwth f PBSiC nanwires by vapr phase reactin thrugh pre channels. During the grwth f the PBSiC nanwires, silica and carbn black pwder reacted with the evaprating silicn mnxide and carbn mnxide vapr inside the pwder surface. At that time, Fe metal catalysts, which were induced by impurities in lw-grade silica, diffused ut f the surface f the silica particles and frmed drplets. Finally, SiC nanwires were synthesized n the surface f the prus bdy with Fe catalysts acting as nucleatin sites. Figure 2 shws the micrstructures f PBSiC (Fig. 2(a), (c)) and SWSiC nanwires (Fig. 2(b), (d)) btained using Fig. 1. Schematic diagram fr the grwth f SiC nanwires n a prus bdy by vapr phase reactin thrugh pre channels. scanning electrn micrscpy. All f the as-grwn SiC nanwires were prepared at 1400 C temperature fr a duratin f 1 h. The PBSiC nanwires grwn n the surface f the prus bdy exhibited a wide variatin in diameter within the nm range and a length f ver 50 µm. Fig. 2(c) clearly shws a liquid drplet at the end f the nanwire, which typically ccurs during VLS grwth. 14) The SWSiC nanwires grwn n silicn wafer ((100) grwth plane) were bserved t have a relatively unifrm diameter f less than 50 nm. The diameter difference in PBSiC nanwires may be due t the silicn mnxide generatin rate that depends n the pre size f the prus bdy. In general, the diameter f the SiC whiskers decreases with increasing silicn mnxide generatin rate 13) implying that this generatin rate is an imprtant prcess factr in device fabricatin. In ther applicatins, it allws fr nanwire handling and enables grwth f structures with high surface area. Figure 3 shws lw-magnificatin TEM images and the crrespnding EDS spectra (inset images) f the SiC nanwires fr impurity analysis. Fig. 3(a) shws the metal tip in the end f the nanwire, which was determined t be Fe. The presence f abut 4.25 wt% f varius metal impurities such as Fe, Mg, Na, Ca, and K was shwn frm a frmal chemical analysis f silica. Amng the impurities, Fe played the rle f catalyst in during VLS grwth. Fig. 3(b) indicates that inner r uter in the nanwires was nt detected ther impurity as well as amrphus and xide layer. Despite the high reactin temperature, the absence f xides is due t the reductin reactin caused by carbn cntained in the raw material.

3 May 2018 Characteristics f Silicn Carbide Nanwires Synthesized n Prus Bdy by Carbthermal Reductin 287 Fig. 2. Micrstructures f as-grwn PBSiC ((a), (c)) and SWSiC nanwires ((b), (d)) (grwn at 1400C fr 1 h). Images were captured using scanning electrn micrscpy. Fig. 3. A lw-magnificatin TEM image and the crrespnding EDS spectra (inset images) f SiC nanwires fr impurity analysis. Figure 4 shws the X-ray diffractin patterns f the PBSiC and SWSiC nanwires prepared by the carbthermal reductin prcess. All the samples culd be indexed t a zincblende structure β-sic (3C-SiC). Fig. 4(a) als shws the presence f anther bdy, which was determined t be silica in a transfrmed crystalline phase (cristbalite) in the prus bdy at high temperature. The intensity rati f the in the PBSiC and XRD peak at 33.6 and 41.4 I /I

4 288 Jurnal f the Krean Ceramic Sciety - Jung-Hun Kim and Sung-Churl Chi Vl. 55, N. 3 SWSiC nanwires was 0.83 and 1.80, respectively. The intensity rati increased with increasing stacking fault cntent. XRD results cnfirmed that the stacking fault density f SWSiC was greater than that f PBSiC nanwires. The HRTEM and SAED (inset in figures) analyses f the PBSiC (Fig. 5(a)) and SWSiC (Fig. 5(b)) nanwires are shwn Fig. 5. The SAED patterns f all samples recrded alng the [110] zne axis shw that the nanwires have cubic zincblende structure with grwth alng the [111] directin. The bright field image and its analysis establish that the PBSiC nanwire has a smth surface with 120 nm diameter. N evident stacking faults r twin defects were fund in the HRTEM image. N streak was bserved in the SAED pattern (see the inset image in Fig. 5(a)) fr this sample, which demnstrated that this nanwire has a nearly perfect single crystalline structure. In cntrast t the PBSiC nanwire, the SWSiC nanwire was fund t have a rugh surface and mre stacking faults. The SAED pattern f the SWSiC nanwire shws sme featureless streaks and spts, which imply that SWSiC has a disrderly layered structure perpendicular t its grwth directin. The abve results imply that an SWSiC nanwire plays an imprtant rle in the frmatin f stacking faults. It culd be explained that the number f stacking faults is related t the nanwire diameter, i.e., the number f stacking faults increases with decreasing nanwire diameter. Accrding t the axial next-nearest neighbr Ising (ANNNI) mdel, SiC whiskers with stacking faults have a lwer energy than thse withut stacking faults. Furthermre, the frmatin f stacking faults prmtes [111] facets, which have much lwer surface free energy than in ther directins, such as [211] r [110]. Therefre, with regards t energetic cnsideratins, the frmatin f stacking faults 15,16) 11) 17) 18) Fig. 4. X-ray diffractin pattern f the (a) PBSiC and (b) SWSiC nanwires prepared by carbthermal reductin. All the samples culd be indexed t a zincblende structure β-sic (3C-SiC). Fig. 5. HRTEM and SAED (inset in figures) images f the (a) PBSiC and (b) SWSiC nanwires.

5 May 2018 Characteristics f Silicn Carbide Nanwires Synthesized n Prus Bdy by Carbthermal Reductin 289 during SWSiC nanwire grwth is favrable due t the cntributin f the stacking faults themselves and the [111] facets at the lateral surface. The specific lateral surface area f the nanwires becmes relatively large when the nanwire diameter is small. This may enhance the frmatin f stacking faults t reduce the cntributin f lateral surface energy. In additin, the free-standing SWSiC nanwires n silicn substrate allw the effect f stress generated due t the lattice mismatch with the substrate t be excluded. Induced stress acts as a driving frce fr defect generatin. The exclusin f stress effects shuld cntribute t the fabricatin f single crystalline SiC nanwires with defects. The result indicates that mre stacking faults can als be frmed in the SWSiC when the diameter is small and stress is generated by lattice mismatch between the nanwires and the substrate. 4. Cnclusins We reprt a large-scale synthesis methd fr SiC nanwires using a prus bdy and silicn substrate fr industrial applicatins, alng with their structural characteristics. SiC nanwires were fabricated frm a lw-grade silica and carbn black pwder using simple carbthermal reductin at high temperature ( C). PBSiC nanwires with varius diameters ( nm), lng lengths ( µm), and high aspect ratis were frmed by reactin f silicn mnxide and carbn mnxide thrugh the prus bdy pre channels. SWSiC nanwires with narrw diameters and mre structural defects were synthesized n a silicn substrate at a lcatin near the prus bdy. All samples were identified as single crystalline β-sic with grwth alng the [111] directin. The grwth mechanism was discussed in terms f VLS. Chemical analysis f metal tip at the end f the nanwire, as seen in the EDS image, cnfirmed the rle f Fe as a grwth catalyst. Fe was induced by impurities in the lw-grade silica pwder. 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