Information storage using nanoscale electrodeposition of metal in solid electrolytes

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1 Superlattices and Microstructures 34 (2003) Information storage using nanoscale electrodeposition of metal in solid electrolytes M.N. Kozicki, M. Mitkova, M. Park, M. Balakrishnan, C. Gopalan Center for Solid State Electronics Research, Arizona State University, Tempe, AZ , USA Available online 20 April 2004 Abstract Programmable metallization cell (PMC) memory is based on the electrochemical control of nanoscale quantities of metal in thin films of solid electrolyte. It shows great promise as an ultrascalable solid state non-volatile memory as it requires low programming voltage and current, and has the ability for the storage cells to be physically sized at minimum lithographically defined dimensions. Scalability issues will be discussed in the context of recent findings relating to the nanostructure of the electrolyte and results obtained from small-geometry devices based on Ag Ge Se nano-phase separated material Elsevier Ltd. All rights reserved. Keywords: Scaling; Programmable metallization cell; Nanoscale phase separation; Chalcogenide glass; Nonvolatile memory 1. Introduction The semiconductor industry has acknowledged, via the International Technology Roadmap for Semiconductors [1], that there will be severe problems with the scaling of solid state memory as we move toward the end of this decade. Physical size reduction of memory based on charge storage (e.g., DRAM, Flash) will result in unacceptable retention or state detection characteristics and the voltage, power, and cost requirements of future systems rule out most other approaches. Programmable metallization cell (PMC) memory, Corresponding author. address: (M.N. Kozicki) /$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi: /j.spmi

2 460 M.N. Kozicki et al. / Superlattices and Microstructures 34 (2003) which is based on the electrochemical control of nanoscale quantities of metal in thin films of solid electrolyte, shows great promise not only as an ultra-scalable but also as a manufacturable solid state memory [2]. Key attributes are low internal voltage, low power consumption, and the ability for the storage cells to be physically scaled to the minimum possible area. Electrolyte formation is a relatively simple process, involving the dissolution of silver in a chalcogenide or oxide glass. Standard processing equipment may be utilized and no high-temperature steps are necessary. A silver-containing anode and an inert cathode formed in contact with the electrolyte creates a device in which information can be stored via electrical changes caused by the oxidation of the anode silver and reduction of silver ions in the electrolyte. This occurs at an applied bias as low as a few hundred mv and can result in a resistance change of many orders of magnitude even for currents in the µa range. A reverse bias of the same magnitude will reverse the process until the excess silver has been removed, thereby erasing the device. Since information is retained via metal atom electro-deposition rather than charge storage, PMC memory is non-volatile with excellent retention characteristics beyond 10 years [2]. Write and erase can be achieved rapidly both occur in the sub-20 ns regime and endurance appears to be good with no apparent degradation up to cycles. An operating window with a wide temperature range is achievable and the cells may be formed using available processing techniques in the metallization layers above the silicon devices in a back end of line (BEOL) process. This paper focuses on the scalability of the technology and presents some recent results involving devices formed using electron beam lithography techniques. Size reduction demands both physical and electrical scalability (low programming voltage and current) and these issues will be discussed in the context of recent findings relating to the nanostructure of the electrolyte. 2. Nanostructure of the solid electrolyte The heart of the PMC memory cell (Fig. 1(a)) is the solid electrolyte and it is the nanostructure of this material that is responsible for many of the operational characteristics. We can form a solid electrolyte which will conduct ions over a wide range of operational temperatures (e.g., 55 to +125 C) by photodissolving silver from a metallic surface source into a thin film of germanium chalcogenide glass until the resulting ternary is chemically saturated with the metal [3]. Photodissolution is achieved using light energy close to the optical gap of the starting glass (typically in the near UV). One acceptable candidate for the hosting glass is Ge x Se 1 x, where x is usually close to Silver uptake ceases when all chemically available Se has reacted to form a separate phase close to Ag 2 Se. The amount of silver required for saturation depends on the composition of the starting glass [3] but the resulting ternary can have silver incorporation in the tens of at.%. The silver significantly modifies the transport properties of the material so that ion mobility is relatively large, in the order of 10 4 to 10 3 cm 2 /V s at room temperature, and the availability of mobile silver throughout the electrolyte is high [4, 5]. Silver is also used as the oxidizable metal in the anode of the PMC device and is particularly good in this respect due to its nobility and the symmetry of oxidation and reduction characteristics [6], so that it is readily added to and removed from the electrolyte.

3 M.N. Kozicki et al. / Superlattices and Microstructures 34 (2003) Fig. 1. (a) Scanning electron microscope image of a PMC memory cell cross section fabricated using PMMA as the dielectric. The Ag Ge Se electrolyte and silver anode are formed in a 100 nm via in the dielectric. (b) Schematic of the nanostructure of the Ag Ge Se solid electrolyte. Electrolyte is nano-phase separated into a dispersed conducting silver-rich phase and a germanium-rich/silver-poor resistive glassy interstitial phase. The average size of the silver-rich phase is around 2 nm whereas the average interstitial gap is less than 1 nm. We have recently established that the electrolyte formed by silver dissolution into a thin film of chalcogen-rich glass is actually a nanostructured material [3, 7], consisting of a finely dispersed low-resistivity silver-rich phase and an interstitial germanium-rich glassy phase that exhibits high resistivity (Fig. 1(b)). In the case of the Ag Ge Se system, the resistivity is around 2 m cm for the silver-rich phase and is estimated to be as high as 10 8 cm for the germanium-rich phase. For a silver-saturated ternary, the glassy interstices between the silver-rich regions have an average width of less than 1 nm but the material s high resistivity makes the electrolyte resistance relatively high, in the order of 10 2 cm for the selenide-based electrolyte. A layered electrolyte, in which the silver concentration is less than 10 at.% within a few nm of the cathode, compared with at.% in the rest of the film; can be created using the photodissolution process and limiting the exposure time. This is useful in that it increases the off resistance of the structure to as much as µm 2 as the low-doped material has an effective resistivity closer to that of the interstitial material [2, 4]. At the nanoscale, each silver-rich region in the current path acts as a local supply of ions. For each excess ion that enters one of these regions from the anode side, one will simultaneously leave on the cathode side and move into the interstitial zone there. Once in this glassy material, the high local electric field will cause the ions to move toward the adjacent downstream silver-rich region. The electron current from the cathode will also flow into the electrolyte and the supply of both ions and electrons in the interstitial zones results in electro-deposition so the excess metal in the electrolyte is effectively stored in these regions. The nanoscale conductive electrodeposits bridge the interstitial regions

4 462 M.N. Kozicki et al. / Superlattices and Microstructures 34 (2003) and help supply electrons to regions further away from the cathode until the bridging to the anode is complete, thereby reducing the resistance between the electrodes. The on characteristics of the PMC memory are determined by the strength of the electrodeposited links the more reduced silver in the linking regions, the lower the effective film resistance. However, the low resistivity of the silver-rich electrodeposits (less than 10 3 cm) mean that a nanoscale link in the order of a few tens of nm in diameter will still result in an acceptable on resistance (less than 100 k ). The existence of this nanoscale connection is confirmed by the fact that the off resistance is a function of device geometry, whereas the on resistance is independent of device area. This insensitivity of on resistance to device area has been established for devices ranging from 5 µm down to 100 nm in diameter [2]. The nanostructure of the electrolyte and the small diameter of the conducting pathway formed by the electro-deposition process mean that the technology will indeed be physically scalable. 3. Device characterization Nanoscale PMC memory devices were fabricated using deep ultra violet (DUV) lithography [2] and also by electron beam patterning of polymethylmethacrylate (PMMA) dielectric. Since the latter is an atypical method, it is described in this section. Silicon substrates with 100 nm thermally grown SiO 2 were prepared and the bottom electrode was defined using standard optical lithography. Approximately 100 nm of Ni was deposited using an e-beam evaporator at ultra high vacuum (UHV) and lifted off to yield the patterned bottom electrode. Electron beam lithography was carried out on this substrate using 100 nm of spin-coated PMMA. A JEOL 6000 e-beam lithographic tool was used to define the nm vias aligned to the bottom electrode. After the via patterns were developed, a layer of photoresist was spun on for the top electrode fabrication. The patterns were transferred using standard optical lithography and after development, the photoresist was completely exposed to ultraviolet radiation in order to facilitate a selective lift-off process using the photoresist developer since the PMMA was soluble in acetone which is traditionally used for lift-off. On this substrate, about 50 nm of Ge 30 Se 70 was evaporated under UHV using a resistively heated Knudsen cell, immediately following this 25 nm of Ag was evaporated without breaking the vacuum. This silver layer was incorporated in the Ge 30 Se 70 glassy matrix by exposing it to UV radiation at 405 nm for about 30 min. A top electrode layer of 25 nm Ag was then deposited using the evaporator. Finally, the samples were treated with photoresist developer to selectively remove the previously exposed photoresist yielding the device with PMMA itself as the dielectric. Fig. 2 shows a typical switching (resistance voltage) characteristic for a 100 nm diameter PMC device with a 50 nm thick Ag 0.33 Ge 0.20 Se 0.47 electrolyte. The sweep was taken using a probe station connected to a semiconductor parameter analyzer (HP 4155C), with a 10 µa current compliance. The off-resistance is around , which although quite high, was lower than expected since larger devices typically with 1 µm via showed an off resistance of greater than A cross-sectional electron microscopic analysis revealed poor step coverage in the small pore. This caused the thinning of the film at the

5 M.N. Kozicki et al. / Superlattices and Microstructures 34 (2003) Fig. 2. Resistance vs. voltage curve of a 100 nm diameter device fabricated using a 50 nm thick Ag-doped Ge Se solid electrolyte. Programming current was 10 µa and the write (switch on) and erase (switch off) thresholds are +240 mv and 80 mv respectively. Off resistance is lower than expected due to poor step coverage in the small-geometry via. via edge which led to the overdoping of the chalcogenide film with silver, thereby reducing the off resistance. The device switches to the on state of just less than 10 k (R on ) at approximately +240 mv (the apparent rise in resistance with voltage following this is due to the current compliance control) and returns to the high-resistance state (R off ) at around 80 mv. The high R off to R on ratio and the demonstrated low programming voltage and current again are proof that the technology is a good candidate for further scaling. In traversing an interstitial glass region, an ion moves less than 1 nm on average. For an applied voltage of a few hundred mv across a film that is a few tens of nm thick, the electric field in the interstitial regions will be around 10 5 V/cm. Since the high-field ion mobility is as high as 10 3 cm 2 /V s, the average ion transit time will be less than 1 ns. Assuming that this is the limiting factor, the rapid ion supply will mean that each interstitial region will have silver deposited in it in 1 ns or less. A write operation that results in a sub- 100 k on resistance will involve multiple nanoscale storage volumes and a combination of sequential and parallel electro-deposition will occur in these regions. Considering the electrolyte nanostructure detailed above, around 20 serial interstitial 1 nm wide volumes will be required in a 50 nm thick film (worst case) for anode to cathode bridging. These will take 20 ns or less to fill assuming that they are filled in sequence. Several hundred interstitial volumes will be involved in fully bridging the interstices in a 50 nm thick film to produce an on resistance in the sub-100 k range but since these will mostly lie in parallel, a sub-20 ns bridging time is still attainable. The same reasoning can be applied in the reverse bias case to predict a sub-20 ns erase time. Fig. 3 gives an example of write erase cycling of a typical PMC device. It was obtained using a simple electrical measurement setup involving a function generator (AWG 2021), digital storage oscilloscope (Tektronix TDS 540B), and a probe station. The characteristics were dominated by the circuit parasitics at 2.3 MHz but device operation (write and erase) is still clear. A ±1 V input signal was required to overcome the measurement system impedance and the output signal, the voltage drop across a 90 k series resistor, was noisy.

6 464 M.N. Kozicki et al. / Superlattices and Microstructures 34 (2003) Fig. 3. Switching and cycling characteristic of a PMC memory cell. The output voltage is measured across a 90 k series resistor. On and off switching is limited by the rise and fall time of the input signal. Input output time shift is due to a 2.8 pf parasitic capacitance. Although the active device area is small, the high capacitance of the contact overlap implies that the output signal would be time shifted. The apparent switching time (both write and erase) is in the order of 35 ns but this is clearly limited by the rise and fall time of the input signal and so it is not unreasonable to assume that the actual switching time is closer to our prediction based on the nanostructural argument. To further confirm this, an arbitrary waveform generator (Tektronix AWG 2021) was used along with the parameter analyzer to create single pulses of 25 ns duration (the fastest the test set-up could reliably handle) and it was observed that these were also sufficient to change the state of the device. 4. Conclusions The prospects for the ultimate scalability of programmable metallization cell memory technology are extremely good. First, the nanostructure of the electrolyte and the small size of the conducting pathway are such that physical scalability well beyond current device structures at 100 nm is thought possible. The low operational voltage and current (240 mv and 10 µa for writing) will also promote scalability as the memory array interconnections can be closely spaced and drive/select transistors can be at minimum geometry. In addition, the speed of the devices means that the overall energy consumption will be extremely low less than 50 fj and this will not only mean low heat dissipation which is necessary for small-geometry/high-density memory arrays but will also equate to longer battery life in portable systems.

7 Acknowledgement M.N. Kozicki et al. / Superlattices and Microstructures 34 (2003) This work is supported by Axon Technologies Corporation. References [1] International Technology Roadmap for Semiconductors: Overall Roadmap Technology Characteristics, Semiconductor Industry Association, San Jose, CA, Available from [2] R. Symanczyk, M. Balakrishnan, C. Gopalan, T. Happ, M. Kozicki, M. Kund, T. Mikolajick, M. Mitkova, M. Park, C. Pinnow, J. Robertson, K. Ufert, Electrical characterization of solid state ionic memory elements, in: Proceedings of the Non-Volatile Memory Technology Symposium, San Diego, CA, November, [3] M.N. Kozicki, M. Mitkova, J. Zhu, M. Park, Nanoscale phase separation in Ag Ge Se glasses, Microelectron. Engrg. 63 (1 3) (2002) [4] T. Kawaguchi, S. Maruno, S.R. Elliott, Optical, electrical, and structural properties of amorphous Ag Ge S and Ag Ge Se films and comparison of photoinduced and thermally induced phenomena of both systems, J. Appl. Phys. 79 (1996) [5] M. Ribes, E. Bychkov, A. Pradel, Ion transport in chalcogenide glasses: dynamics and structural studies, J. Optoelectron. Adv. Mater. 3 (3) (2001) [6] K.H. Ng, H. Liu, R.M. Penner, Sub-nanometer silver clusters exhibiting unexpected metastability on graphite, Langmuir 16 (2000) [7] M. Mitkova, M.N. Kozicki, Silver incorporation in Ge-Se glasses used in programmable metallization cell devices, J. Non-Cryst. Solids (2002)