Advanced Metrology for Copper/Low-k Interconnects

Transcription

1 Advanced Metrology for Copper/Low-k Interconnects Executive Summary The semiconductor industry s continued push to reduce feature size and increase circuit speed has resulted in a global race to reinvent the interconnect structure on the integrated circuit, replacing aluminum and SiO 2 with less-resistive copper metallization and less-capacitive low-k dielectrics. As the industry moves to adopt copper and low-k as the interconnect materials of choice for leadingedge applications, a host of new manufacturing challenges are arising. These challenges stem not just from the introduction of new materials into the interconnect fabrication process, but also from the inherently more complex nature of the manufacturing steps required to work with these materials. This complexity creates a strong need for metrology techniques able to measure copper and associated metal films directly on product wafers in a variety of fine-pattern structures. At the same time, the increasing cost of semiconductor manufacturing, due to the introduction of new materials and the move to 300 mm wafers, is fueling a desire for metrology that can be applied in high volume to enable advanced process control and reduce cost. Philips Advanced Metrology Systems, a business unit of Philips Electronics, was created to provide metrology solutions specifically for copper/low-k interconnect process development and manufacturing. Philips AMS uses proprietary SurfaceWave TM technology for thin film measurement based on laserinduced surface acoustic waves. Originally developed at MIT and exclusively licensed to Philips, the technology permits non-contact, non-destructive measurement of metal and dielectric films with applications targeting all steps of the copper process. Having proven the technology with installations at major chipmakers and OEMs and through work with strategic industry partners, Philips AMS is now poised to provide the semiconductor industry with a low cost-of-ownership solution for copper/low-k film metrology from pilot process development through high-volume production. The Challenges of Copper Reinventing the Interconnect Structure Year after year, the semiconductor industry has created chip designs with higher circuit density and faster performance. The traditional approach to scaling the chip was to reduce all dimensions while basically relying on the same materials: SiO 2 for the gate dielectric at the transistor level, aluminum and SiO 2 as the conductor and insulator at the interconnect levels. Chip speed was dominated by effects at the transistor level, rather than by the interconnects. But this run came to an end when the interconnect delay became a significant contributor to the overall circuit speed. Switching to copper wiring, with lower Copyright 2003, Philips Advanced Metrology Systems, Inc.

2 electrical resistance than aluminum, gives a significant boost to interconnect performance. Copper was first introduced in leading-edge chips in 1998, and is rapidly being adopted by all major manufacturers for high-end products. To further boost performance, the traditional interconnect insulator of SiO 2 is being replaced by a progression of low-k dielectric materials yielding lower capacitance, allowing tighter spacing of wires. The copper and dielectric materials are layered in a complex stack with increasing number of layers, as shown on the left in Figure 1. Dielectric Etch Dielectric Deposition Copper Barrier/Seed Deposition Copper CMP Copper ECD ECD Figure 1. Left: cross-section sketch of an integrated circuit, showing interconnect structure with copper embedded in a dielectric material. (Source: International Technology Roadmap for Semiconductors). Right: Schematic process flow for copper-based interconnect fabrication. Fabrication of copper interconnects is very different from aluminum, and requires different equipment and processes. Aluminum is patterned with a subtractive method, in which the metal films are deposited as a blanket across the wafer, then patterned and etched, with subsequent deposition of insulating dielectric to fill the gaps between the etched metal lines. However, no practical etching techniques are known for copper. Therefore, copper interconnects are fabricated with a Damascene process, in which the copper is embedded in trenches etched into the dielectric. The process steps for fabricating each metal level are illustrated on the right side of Figure 1. First the dielectric layer is deposited and then etched to create a pattern. Next a barrier metal and overlying copper seed layer are deposited across the wafer, using Physical Vapor Deposition (PVD). The barrier metal, typically Ta-based, prevents copper diffusion into the insulator and silicon, and also provides an adhesion layer for the copper seed. Copper electrochemical deposition (ECD) is then used to complete the filling of the etched pattern. Finally, the wafer is polished with chemical-mechanical planarization (CMP) to remove the copper overburden. Why Copper Process Control is More Difficult The introduction of any new materials and equipment into a manufacturing process is generally problematic, as process engineers gain experience with the new processes and work out integration issues. However, beyond the newness factor, there are several issues that make it inherently more difficult to control film thickness uniformity in a copper process than in an aluminum one. Among them: Pattern-specific behavior In an aluminum process, the metal is first deposited across the wafer and then etched and patterned. As a result, the uniformity of the metal thickness across the wafer does not depend on the details of the pattern. Monitoring the performance of the metal deposition equipment on blanket monitor wafers with a contact metrology such as four-point probe is sufficient. However, for copper the film thickness may depend greatly on the local details of the die pattern. For example, the electroplating overburden may be different over arrays of lines than over wide features. Similarly, CMP performance varies with feature type due to the variability of dishing and erosion. (See Philips Advanced Metrology Systems July

3 Figure 2.) As a result, metrology must be performed on patterned wafers to get an accurate picture of the film thickness results. Furthermore, engineers must expend tremendous effort to optimize ECD and CMP processes for different pattern combinations, and rapid on-pattern metrology is needed to streamline this optimization process. Interactions between process steps Fabrication of copper interconnects requires three different metal process steps in sequence in three different tools. Non-uniformity in the deposition of the copper seed layer will affect the uniformity of the electroplating. Similarly, non-uniformity of the electroplating will affect the uniformity of CMP. Integrating all three processes creates an extra challenge. There is a strong desire to be able to use metrology to determine the output of the barrier/seed or ECD step in order to adjust the next process step to compensate for incoming nonuniformities. Wafer-to-wafer process variations In copper CMP, the state of the process tool changes slightly for almost every wafer polished, due to the gradual degradation of the polishing pad and slurry and the fact that the polishing pad must constantly be reconditioned. Similarly, the ECD step may show variability due to gradual changes in the electroplating bath, which contains a complex balance of chemical additives. As a result, there is less stability in the copper process. ECD CMP Dishing Overburden Erosion Figure 2. Pattern-specific effects in copper ECD and CMP processes. It s Not Just Copper It is important to remember that there is more to the copper process than just copper. A copper interconnect process includes other materials, which add their own production and metrology challenges: Tungsten At the transistor contact level, narrow tungsten plugs are used to form a link from the transistor to the copper interconnect structure (see Figure 1). These features have the finest dimensions in the interconnect stack. As circuit dimensions shrink, contact plug aspect ratios increase and it becomes more difficult to fill the structures without voiding. Metrology capable of measuring arrays of submicron plugs is therefore required for process control. Barrier metals Barrier metals, typically Ta or TaN, are used to encapsulate the copper in the dielectric trenches. Again, as circuit dimensions shrink, there are additional demands placed on the processing of these metals. In particular, continued circuit scaling requires that barrier metals be deposited in much thinner layers, to reduce series resistance at via bottoms, and with greater conformality, to coat the sidewalls of high aspect ratio features. These requirements are driving the aggressive development of new chemical-vapor deposition (CVD) and atomic-layer deposition (ALD) techniques for barrier film deposition. The development of these film processes creates more demands for metal film metrology techniques that can be used for process characterization and monitoring on very thin metal films. Low-k dielectrics Reducing the electrical resistance of the interconnect by incorporation of copper is only half the battle. Getting the highest performance requires adoption of low-k insulators. But lowk materials have a host of materials and integration issues, due to the weaker mechanical strength of the films and the incorporation of porosity into the most advanced low-k materials. Every major chipmaker has struggled with the selection of a low-k material and its successful implementation in production, as evidenced by the delay of widespread low-k adoption from the predicted 130 nm node to at least the 90 nm node. A new and critical metrology parameter not present before low-k Philips Advanced Metrology Systems July

4 adoption is the dielectric film stiffness. This has created a further demand for metrology to aid process engineers in characterizing and monitoring low-k films. Production Problems Given the above challenges, the engineers implementing a copper/low-k interconnect architecture have a number of film metrology issues to worry about in process development and production, including: Low-k material properties Selecting and characterizing a low-k material with adequate mechanical strength and other properties, and monitoring the material in production. Metal film deposition uniformity Keeping each of the metal deposition steps uniform, dealing with interactions between barrier/seed and electroplating, and dealing with the pattern-specific effects of electroplating. Fill voiding Ensuring that the electroplating uniformly fills the trenches, without leaving voids. Copper resistivity Monitoring the electroplating process to make sure that processing conditions, including additive concentration and annealing, produce a film with desirable electrical properties. CMP parameter optimization Choosing the right combination of CMP tool parameters to optimize performance for the specific pattern layout to be processed. Dishing and erosion Minimizing metal loss in wide areas (dishing) and arrays (erosion) during copper CMP. Residual metal Ensuring that no copper or tantalum remains after CMP, which would short the circuit or cause reliability problems. These issues all create a strong demand for new film metrology techniques. Why the Copper Process Requires a New Metrology Approach The advent of the copper and copper/low-k era creates not only additional demands for film Film Metrology Requirement Aluminum/SiO 2 Process Copper/Low-k Process metrology, but demands for new Metal film thickness kinds of film metrology that were Oxide film thickness On-product measurement $ not available or not required for Metal line and via arrays aluminum/sio 2 processes. (See thickness Table 1.) Metal thickness above For an aluminum process it low-k dielectric was sufficient to measure metal film Low-k dielectric thickness thickness with four-point probe on blanket monitor wafers, because the Low-k dielectric stiffness deposition uniformity was not Table 1. Film metrology requirements for aluminum/sio 2 processes pattern-specific. Dielectric film vs. copper/low-k. metrology of the interconnect structure consisted primarily of oxide thickness measurement with transparent film tools such as reflectometers or ellipsometers. While on-product measurement of metal film was not a requirement for aluminum processes, laser-sonar techniques providing this capability were nonetheless introduced for aluminum production in the late nineties. This did provide additional capability, at additional cost, that could in principle be used Philips Advanced Metrology Systems July

5 to reduce monitor wafer consumption. It also provided niche capabilities, such as the ability to measure the multi-layer metal film structure consisting of Al, Ti, and TiN. For copper production, however, on-product measurement becomes not just a cost-saving tool but also a metrology requirement, due to the pattern-specific nature of copper processing. While four-point probe measurement on blanket monitor wafers remains an important tool for characterization of metal film deposition systems, additional tools are needed. Laser-sonar was initially adapted from aluminum applications to copper to fill these new needs, requiring modification of the instrument designs and analysis. However, process engineers have struggled with applying the method to copper, and not all the requirements of Table 1 are met. While laser-sonar does measure metal in field areas on patterned wafers, using it to measure patterned structures such as arrays of lines and vias the features for which copper processing is particularly unique has been and remains a difficult challenge. Additionally, the technique struggles with copper on low-k films. In the dielectric area, transparent film optical measurements such as reflectometry and ellipsometry have been successfully adapted to measure low-k film thickness, although these films do bring additional challenges. However, there are also new metrology requirements for low-k films, such as characterization of film stiffness and other properties, which are not addressed by these metrologies and for which non-contact, non-destructive measurement techniques are desired. All of these factors combine to create a strong demand for new film metrology tools for the copper/low-k era. Philips AMS Philips Advanced Metrology Systems (AMS), a business unit of Philips Electronics, was created to address this growing need for non-contact, small-spot metrology for copper/low-k interconnect process development and production. AMS uses proprietary SurfaceWave TM technology to measure metal and dielectric films using laser-induced surface waves. The technology was originally developed at MIT and exclusively licensed to Philips in Philips has further developed the technology to specifically focus on applications for copper/low-k interconnects. Years of development have yielded a highly refined technology, now in its third generation. The technology has been proven through application at fab, foundry, and OEM installations and with Philips s strategic industry R&D partners. AMS was launched as a new business unit of Philips in 2003 to bring the SurfaceWave TM technology to the wider market on newly developed platforms for 200 and 300 mm facilities. SurfaceWave TM Technology Non-Contact Measurement Using Surface Waves The basics of the SurfaceWave TM technology are simple. Laser excitation is used to create an acoustic wave that travels along the surface of a sample film. A probe laser detects the passing wave. Computer analysis of the wave speed and other characteristics of the signal waveform are used to determine film thickness or other sample properties. The main principle is that the presence of a film on a substrate will change the speed of an acoustic wave traveling along the sample surface. Figure 3 illustrates the technique in more detail. Since the detector is off the axis of the reflected probe beam (panel 1), the detector does not register any signal until the acoustic wave is created, so the measurement is done against a dark background, yielding a high signal-to-noise ratio. A short pulse of laser light (532 nm) is used to excite an acoustic wave of fixed wavelength using a striped pattern, and this wave travels laterally in the film (panel 2). The probe laser light (830 nm) diffracts off the passing wave, and the detector registers the diffracted signal intensity (panel 3) versus time. A typical signal Philips Advanced Metrology Systems July

6 Figure 3. Schematic diagram of the SurfaceWave TM technique. waveform is shown in Figure 4, with the waveform s 180 Cu film 3.0 frequency spectrum shown in the inset. Analysis of the F frequency spectrum is used to determine wave speed 120 and to calculate film thickness F 2 While the basics of the technique are simple, the waveforms contain a rich set of information Analysis of secondary characteristics, such as decay rates and other features, can be used to determine more Frequency (GHz) 0 information about the film stack As an in-fab metrology technique, SurfaceWave TM Time (ns) has several important advantages. The Figure 4. Typical SurfaceWave TM signal system uses compact solid-state lasers and is waveform acquired on a copper film. vibration-tolerant, making it highly robust. In addition, the high signal-to-noise ratio of the technique means measurement is fast, with typical data acquisition times of ~1 second per site, significantly faster than the nearest competitors. The robust apparatus and the short measurement time combine to make the cost-of-ownership of a SurfaceWave TM tool very competitive with other options. Metrology Developed for the Copper Process SurfaceWave TM was specifically developed with the copper film metrology requirements of Table 1 in mind. It provides the ability to measure not only metal field areas of product wafers, but also arrays of finely patterned features such as lines and vias. This allows it to be applied to pattern-specific process development issues arising from metal deposition and CMP. It is able to measure both copper and its associated metals (tungsten, tantalum, tantalum nitride, etc.) on both SiO 2 and low-k dielectrics. And it provides capability to measure dielectric thickness or properties such as film stiffness. The application range of SurfaceWave TM is illustrated in Figure 5, showing the capabilities the method provides at each film processing step of the interconnect fabrication cycle. Philips AMS has developed these applications of SurfaceWave TM technology to address major film process issues at each fabrication step, from dielectric deposition, through barrier/seed, plating, and CMP. While other metrology tools are dedicated to specific subsets of the fabrication sequence, Philips AMS is able to offer a wide range of functionality. This versatility in the metrology tool brings an additional benefit: greater value per tool. Due to the increasing cost of all process and metrology equipment, it is important for every new piece of equipment to be as versatile as possible. Engineers are seeking to combine functionality into fewer tools to keep budgets under control. Signal (mv) FFT Power (arb) Philips Advanced Metrology Systems July

7 Figure 5. SurfaceWave TM technology covers a wide range of applications for copper/low-k interconnects, meeting the specific film metrology requirements of the copper era. From Pilot Through Production Scaling Up with the Process Process engineers need metrology tools at both the early and late stages of their work. During the early stage, development and pilot process implementation, metrology is needed to allow rapid characterization of film process issues. Here the speed and small spot size of the SurfaceWave TM measurement provide special value. Because SurfaceWave TM can measure sites very quickly, it enables full-wafer mapping capability that gives the engineer additional perspective on the process issues. This is particularly true for copper development, where pattern-specific effects of ECD and CMP require repeated studies on test patterns to determine optimum process parameters. The SurfaceWave TM capability to rapidly measure the line and via array structures used in these optimizations gives the engineer a unique development tool. In the late stage of development, when a process is entering pilot or full production, metrology is equally important to monitor film process equipment and ensure stability of the results. Here repeatability, ease-of-use, and throughput are the most important factors. SurfaceWave TM is ideally suited for this production monitoring, due to the robust nature of the apparatus, short measurement time, and simplified analysis. These various characteristics of SurfaceWave TM therefore meet an important requirement: they allow the user to move the metrology tool from development into production as their process matures. Advanced Process Control As the semiconductor industry matures, there is an increasing desire to employ metrology not only for trouble-shooting or conventional process control requiring human intervention, but also for advanced process control (APC) real-time feedback and feedforward of metrology data for automated Philips Advanced Metrology Systems July

8 adjustment of process equipment. This promises to reduce manufacturing cost by keeping process tools in better control. The logical extension of APC is to include metrology systems integrated directly into a process tool, where the metrology can be used to monitor a high fraction of the processed wafers without significantly reducing overall throughput or increasing footprint. Integrated metrology also allows the engineer to more readily qualify a process tool for production after preventative maintenance. In order for APC and integrated metrology to succeed in a particular application, the metrology tool must be robust, highly repeatable, and compact. Philips AMS has positioned its SurfaceWave TM technology to meet all these needs for integration of the SurfaceWave TM measurement head into metal film processing tools. Summary The adoption of copper and low-k dielectrics poses new manufacturing challenges that require new film metrology approaches and equipment. The metrology needs for copper/low-k interconnects are different and more complex than for aluminum-based processes. Philips Advanced Metrology Systems was created to provide non-contact SurfaceWave TM film metrology for copper/low-k interconnects. SurfaceWave TM technology responds to the specific film metrology needs of the copper/low-k era, and addresses a wide range of process development and production issues for each step in the interconnect fabrication process. The AMS technology is positioned to enable the process engineer to move metrology equipment applications easily from development to pilot to production. This is accomplished with robust equipment, high-speed and high-repeatability measurement, and simple analysis. Philips Advanced Metrology Systems July

9 Philips Advanced Metrology Systems Contact Information Bill Gately General Manager Philips Advanced Metrology Systems 12 Michigan Drive, Natick (508) Chris Moore Product Support Manager Philips Advanced Metrology Systems 12 Michigan Drive, Natick (508) About Royal Philips Electronics Royal Philips Electronics of the Netherlands, the parent company of Philips AMS, is one of the world's biggest electronics companies and Europe's largest, with sales of $30.1 billion (EUR 31.8 billion) in It is a global leader in color television sets, lighting, electric shavers, medical diagnostic imaging and patient monitoring, and one-chip TV products. Its 170,000 employees in more than 60 countries are active in the areas of lighting, consumer electronics, domestic appliances, components, semiconductors, and medical systems. Philips is quoted on the NYSE (symbol: PHG), London, Frankfurt, Amsterdam and other stock exchanges. News from Philips is located at Philips Advanced Metrology Systems July