p -substrate (lightly doped) photoresist p -substrate (lightly doped) SiO2 SiO2 p p -substrate (lightly doped) SiO2 SiO2

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1 EE143 S2006 Homework Assignment #10 Solutions * It is understood hotoresist has to be removed rior to high-temerature rocessing stes. This is stated exlicitly in the rocess flow only if the hotoresist is used as an imlantation mask. Problem 1 1) Starting material PROCESS DESCRIPTION CROSS-SECTION -substrate (lightly doed) 2) Thermal oxidation to grow ad oxide CVD Si 3 N 4 Pattern active device area (Mask #1) hotoresist ad oxide -substrate (lightly doed) 3) Channel sto imlant (boron) Remove hotoresist Thermal oxidation to grow field oxide ad oxide -substrate (lightly doed) 4) Stri Si 3 N 4 Stri ad oxide with HF di Threshold imlant (if necessary) Thermal oxidation to grow gate oxide CVD 1st level oly-si Pattern 1st level oly-si (Mask #2) -substrate (lightly doed) 5) Thermal oxidation of 1st level oly-si CVD 2nd level oly-si Pattern 2nd levle oly-si (Mask #3) 2nd oly hotoresist -substrate (lightly doed)

2 6) As imlant through thin oxide to form self aligned source Remove hotoresist Post-imlantation annealing 2nd oly -substrate (lightly doed) 7) CVD of Pattern contact oening to 2nd-level oly-si (wordline), source (bitline), and 1st level oly- Si (caacitor ground lane). Mask #4. The latter two are not shown in this cross-section. CVD 2nd oly -substrate (lightly doed) 1st oly 8) Al deosition and metal atterning (Mask #5) CVD 2nd oly Al thermal oxide 1st oly -substrate (lightly doed) Comments It is extremely difficult to attern the narrow sacing (<30nm) using lithograhy because of alignment error and minimum resolution issues. This examle use the controllable thermal oxididation rocess to fabricate this ga sacing. Problem 2 Ste 4 CROSS-SECTION ALONG A-A' ad oxide CROSS-SECTION ALONG B-B' ad oxide - substrate - substrate Ste 8 ad oxide ad oxide - substrate - substrate 2

3 Ste 21 oly Si mask oxide mask oxide - substrate - substrate Ste 27 oly Si Al CVD - substrate CVD - substrate Ste 32 oly Si Al CVD - substrate CVD - substrate Problem 3 The following is a solution based on a dummy gate concet. Other variations are ossible. Staring material: -Si 1) LOCOS 2) Deosit 0.5 µm oly-si or other high-melting oint material (e.g. Si 3 N 4,silicides etc) 3) Pattern oly-si to gate dimension 4) Blanket As imlantation. Post-imlantation annealing oly-si 5) Deosit sin-on-glass or to lanarize surface 6) Etch back to to of oly-si substrate oly-si CVD Glass substrate 7) Selectively etch oly-si 8) Grow gate oxide 3

4 CVD Glass substrate 9) Directional deosition of Al (level-1) (e.g. collimated suttering). * another alternative is deosit a very thick layer of Al and then use CM to olish back to the CVd glass level. Al (level-1) CVD Glass substrate 10) Use highly selectively wet etch to remove CVD glass substrate 11) Deosit by CVD 12) Contact oening substrate 13) Al (level -2) deosition 14) Al atterning Al ( level 2) Al ( level 1) substrate [Comment] If imlantation is not required, we can also for the self-aligned S/D by diffusion. the following is an alternative : Use as doing source to form source/drain 4

5 CVD Glass substrate Gate oxide growth CVD Glass substrate Directional Al gate deosition (e.g. collimated suttering) Al (level-1) CVD Glass substrate Stri... continue as above rocess Problem 4 (a) PROCESS DESCRIPTION CROSS-SECTION TOP VIEW 1) Starting Material No lateral feature 2) CVD 1st level CVD 1st level oly-si 1st level oly Si 1st level No lateral feature 3) Pattern 1st level oly-si (Mask #1) 1st level oly Si 1st level (1st oly) 4) CVD 2nd level 2nd level 1st level oly Si 1st level (1st oly) 5

6 5) Pattern oening for fixed in (Mask #2) 2nd level 1st level oly Si 1st level (1st oly) 6) CVD 2nd level oly-si Pattern 2nd level oly-si (Mask #3) 7) Selectively etch away 1st level and 2nd level with HF. Final Structure 2nd level 2nd level oly Si 2nd level oly Si 1st level oly Si 1st level oly Si freed and can rotate around stationary in stationary (2nd oly) free sinning (1st oly) s t a t i o n a r y f r e e ( 2 n d o l y ) s i n n i n g ( 1 s t o l y ) (b) (I) If hotoresist is used to relace oly-1 as the rotor material, it cannot withstand the rocessing temerature ( o C)of the subsequent CVD stes. (II) In rincile, yes. Thermal oxide will be grown conformally on all surfaces and sidewalls of the oly-1 rotor and the oen hole of the Si susbstrate. After fix in contact oening, oly-2 deosition and atterning, HF can still enetrate all sacrificial oxides (thermal oxide and ) surrounding the oly-1 rotor and release it. In ractice, not a desirable rocess. Thermal oxide growth rate is too slow and requires a high temerature. The oxide grown will also consume oly-si. Thickness of oly-si will be reduced and final dimension of the rotor inner hole will be distorted (larger). Uneven oly-si oxidation rates along grain boundaries may leave a rougher edge which may increase the friction between rotor and in. (III) NO with the resent rocess methodology. The to of the in has to be larger than the inner hole of the rotor to kee the rotor from falling off the wafer. The in dimension has to be atterned with a searate lithograhy ste. [ Comment: If one oens a hole in -1, deosit oly-1, and attern oly-1 for both rotor and in with same lithograhy ste, the in and rotor will not be connected. However, the rotor will fall out of the wafer after etching the sacrificial oxide.] Problem 5 1) Starting structure ( oxide trench isolation) -Si 2) Pad oxide growth. CVD nitride. Pattern to smallest feature allowed by Otical lithograhy. Etch stack. nitride -Si Pad oxide 3) Angle imlant of As to form ockets. 6

7 nitride Angle imlantation Angled Imlant ocket Pad oxide 4) Vertical imlant of As to form normal S/D nitride Angled Pad oxide Imlant ocket Normal S/D imlant 5) Blanket deosition of ure Ti. Anneal at 750C to form. Remove unreacted Ti on oxide and nitride. Additional anneal (900C) to activate S/D imlant. nitride Angled Pad oxide Imlant ocket Normal S/D imlant 6) Blanket nitride Angled Pad oxide Imlant ocket Normal S/D imlant 7

8 7) Planarize structure to nitride surface with CMP. nitride Angled Pad oxide Imlant ocket Normal S/D imlant 8) Selective etch of nitride. Slight di in HF to remove ad oxide. Blanket. Use anisotroic RIE to form oxide sacer. Oxide sacer Normal S/D imlant Angled Imlant ocket 9) Grow thermal gate oxide. Deosit doed oly-si by CVD Pattern oly-gate. Oxide sacer Smallest feature rintable by otical lithograhy oly-si gate Normal S/D imlant Angled Thermal Imlant gate oxide ocket 8