Characterization and Improvement of Reverse Leakage Current of Shallow Silicided Junction for Sub-100 nm CMOS Technology Utilizing N 2 PAI

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1 Journal of the Korean Physical Society, Vol. 49, December 2006, pp. S795 S799 Characterization and Improvement of Reverse Leakage Current of Shallow Silicided Junction for Sub-100 nm CMOS Technology Utilizing N 2 PAI Kyong-Jin Hwang, Jong-Hyuck Oh, Nag-Kyun Sung, Doo-Yeol Ryu, Seung-Hoon Sa, Kun-Joo Park, Jong-Kon Lee and Jeong-Gun Lee Process Development Team 3, Magnachip Semiconductor Ltd., Cheongju Sung-Hyung Park, Tea-Gyu Goo and Hi-Deok Lee Department of Electronics Engineering, Chungnam National University, Daejeon (Received 23 February 2006) This paper presents the mechanism of junction leakage current for shallow n+/p junctions using a Co-silicide process. An abnormal leakage current occurred for a perimeter intensive diode. The main cause of the increased leakage current is not the formation of a Schottky junction, but the cobaltsilicide-related traps near the junction. Poole-Frenkel barrier lowering predominantly influenced the reverse leakage current, thereby masking the Schottky contact effect. Reverse leakage current can be reduced by using N 2 Pre-Amorphization Ion implantation (PAI) before the Co-silicide process for nano-scale CMOS technology. It was revealed that nitrogen atoms can retard the diffusion of cobalt atoms. PACS numbers: Tv, Kk Keywords: Junction leakage current, Shallow junction, Salicide, Poole-Frenkel barrier lowering, PAI I. INTRODUCTION The salicide (Self-Aligned silicide) technology has become one of the main issues for 0.25-µm CMOS logic devices and beyond. Co-salicide has been widely used for deep submicron devices because of a small narrow line effect and relatively good thermal stability of sheet resistance [1]. However, shallow junctions with Co-salicide are known to have a serious junction leakage problem due to the short distance between the bottom of the silicide and the junction edge, due to the large silicon consumption during silicidation [2]. However, an ultra-shallow junction is inevitable to suppress the short-channel effect and device punch-through in nano-scale CMOSFETs [3], [4]. Therefore, silicidation on the shallow junction becomes more and more difficult as the scale-down of the MOSFET continues [5]. Moreover, sheet resistance of Co-silicide can be dramatically increased due to thermal grooving and agglomeration of the silicide into discrete islands because of high-temperature processes after silicide formation [6]. Much research has been done to reduce the problems, and Pre-Amorphization Ion implantation (PAI) prior to the silicide formation is suggested as one of the solutions [7,8]. In this paper, it is shown that N 2 PAI prior to the deposition of the metal layers for silicidation is efficient to hdlee@cnu.ac.kr; Fax: reduce reverse leakage current and to improve the thermal stability of the formed CoSi 2. The main mechanism of junction leakage current is characterized as the Poole- Frenkel barrier lowering due to the Co-related traps near the junction. From the physical analysis, it is found that the nitrogen retards the diffusion of Co toward the junction region and hence reduces the junction leakage current. It is also shown that a shallower junction formed at the active edge can be more deteriorated in terms of increased junction leakage current. II. DEVICE FABRICATION Sub-100-nm CMOS technology was used to fabricate n+-p junctions on p-type (100) silicon substrate with resistivity of 9 12 Ω-cm, and key processes and their process conditions are summarized in Fig. 1. After formation of Shallow Trench Isolation (STI), the n+/p-well (n+-p) junction is formed by using low-energy implantation of boron (well) and arsenic (S/D), respectively. After formation of the n+-p junction and HF cleaning, S/D RTA was carried out for dopant activation. A N 2 PAI process was also carried out as split to suppress the agglomeration of Co-silicide on the n+-p junction. 12-nm-thick Co films were sputter-deposited and 25-nmthick Ti films were also sputtered without breaking the vacuum as a capping layer. Co-silicide was formed by a -S795-

2 -S796- Journal of the Korean Physical Society, Vol. 49, December 2006 Fig. 1. Process flows for fabrication of the n+/p junctions. Fig. 2. Cumulative probability of reverse leakage current of n+/p junctions with different silicidation splits. Junction leakage current is measured at 1.2 V. two-step rapid thermal process (RTP). The 1 st RTP was performed at a temperature of 500 C in a N 2 ambient. After the 1 st RTP, the unreacted metals were selectively removed by SC1 and SC2 cleaning. Then, the 2 nd RTP was carried out at 750 C in a N 2 ambient. The thickness of the CoSi 2 layer was about 350 nm. Next, intentional thermal stress was applied for some wafers at 950 C for 30 sec in N 2 ambient to check the thermal stability of Co-silicide. Shallow junctions without Co-silicide were also fabricated for comparison. There are two kinds of junction diodes, namely, an area pattern consisting of a square of 270 µm 372 µm and a perimeter pattern comprising 310 rectangles of 270 µm 0.6 µm connected in parallel. Current-voltage characteristics were measured with forward bias of 0 1 V and a reverse bias of 0 6 V by using a HP4155 semiconductor parameter analyzer at various temperatures from 20 to 180 C. Physical characteristics of Co-silicide and junction profile were analyzed by using Secondary Ion Mass Spectrometry (SIMS), Scanning Capacitance Microscopy (SCM), and Transmission Electron Microscopy (TEM). III. RESULTS AND DISCUSSION 1. Junction Leakage Characteristics with/ without Co-salicide and N 2 PAI The cumulative probabilities of the reverse leakage current for all types of n+/p junctions are shown in Fig. 2. The leakage current is measured at 1.2 V. For all types of diode, a normal silicided junction shows the highest junction leakage current and the widest current distribution, while the N 2 PAI process shows improved leakage current level and distribution. Fig. 3 shows I V Fig. 3. I-V characteristics of n+-p junction diodes in the reverse bias region at a temperature of 25 C. The diodes show strong voltage dependence, regardless of the splits. characteristics of the diodes in the reverse bias region. The measured die in the wafer is 50 % of the cumulative probability point in Fig. 2. The reverse leakage currents of silicided junctions with and without N 2 PAI show stronger voltage dependence than that of a non-silicided junction for both area and perimeter diodes, and a silicided junction without N 2 PAI shows stronger dependence of leakage current on reverse bias than the N 2 PAI case. Ideally, n+-p junction leakage current should depend on the square root of the applied voltage [9]. Therefore, it can be said that the silicide process greatly affects junction properties. The exponential voltage dependence of junction leakage current suggests field-enhanced carrier transport in the reverse biased junction, as will be detailed later. Arrhenius plots of the leakage current for all types of diode were used for characterizing the junction properties, as shown in Fig. 4. The reverse leakage current was measured at 1 V in the temperature range of

3 Characterization and Improvement of Reverse Leakage Kyong-Jin Hwang et al. -S797- Fig. 4. Arrhenius plots of (a) area-type, and (b) perimeter-type diodes, measured at 1 V. The values in figures are activation energies (ev). C. The temperature dependence of the reverse leakage current as revealed by the slope of the Arrhenius plot provides a useful insight into the mechanisms for reverse junction leakage current [9]. The activation energy (E a ) of reverse leakage current is close to the silicon energy band gap (E g ) when the reverse current is dominated by diffusion current and close to half the silicon energy band gap (E g /2) when dominated by generation and recombination. Fig. 4 shows that in the low-temperature region, the activation energies (E a ) of all the diodes are quite different. Especially, the perimeter type diode (Fig. 4(b)) shows that the Ea strongly depends on silicidation scheme. Ea of the normal-silicide junction is about 0.32 ev, and this is much lower than E g /2. This means that the leakage current is not dominated by generation and recombination, but by an other mechanism, which is believed to be the Poole-Frenkel barrier lowering due to the silicide-induced traps in the junction [10]. The E a of reverse leakage current and current dependence on reverse bias have a similar tendency according to silicide formation scheme and diode type. The dependence of leakage current on reverse voltage as in Fig. 5 and 6 can suggest Poole-Frenkel barrier lowering or Schottky barrier lowering operative in the junction depletion region. So, the mechanism of the reverse leakage current (I R ) can be investigated by using the slopes of I R /E versus E 1/2 for Poole-Frenkel barrier lowering or I R / T 2 versus E 1/2 for Schottky barrier lowering. Fig. 5 and 6 show I R /E vs. E 1/2 and I R / T 2 vs. E 1/2 curves, respectively, derived from the data of Fig. 4. In Fig. 5, the slopes are relatively similar to the theoretical value ( (V/cm) 1/2 ) for the Poole- Frenkel effect, but the slopes in Fig. 6 are much larger than the theoretical value ( (V/cm) 1/2 ) for Schottky barrier lowering. In Fig. 5, some of the slopes in the perimeter type are much larger than (V/cm) 1/2, which is presumably due to high doping of the p-well and the trap assistance tunneling effect. Therefore, it can be said that Poole-Frenkel barrier lowering is responsible for the large reverse leakage current in shallow junction with Fig. 5. I R/E versus E 1/2 plot for the Poole-Frenkel barrier lowering. The slope of each curve is shown in the low-electricfield (E) region at 25 C. Fig. 6. I R/T 2 versus E 1/2 plots for Schottky barrier lowering, where the slope of each curve in the low-electric-field (E) region is shown at 25 C. Co-silicide.

4 -S798- Journal of the Korean Physical Society, Vol. 49, December 2006 Fig. 7. Current-voltage plot in the forward bias region at 25 C. The numbers in the figure denote the ideality factor obtained in the low-voltage region. Fig. 9. Typical SCM image for perimeter type diode junction, showing 2-D dopant profiles. It is notable that the profile bends upward near the edge of the active region. Fig. 10. Typical TEM images of perimeter type diode without N 2 PAI: (a) before, and (b) after 30-sec thermal stress twice at 950 C. Fig. 8. SIMS profile of n+ S/D regions. The analysis of the I-V curve in the forward-bias region is an effective method to characterize the junction properties when silicidation affects the reverse leakage current [9]. The ideality factor (n) is obtained in the low-voltage region from Fig. 7. In the area-type diode, the ideality factor for the non-silicided junction and the silicided junction with and without N 2 PAI is 1.03, 1.07, and 1.07, respectively. In the case of the perimeter-type diodes, the ideality factor for the three junctions is 1.40, 1.43, and 1.52, respectively. As is well known, n is close to 1 when the forward current is dominated by diffusion current and close to 2 in the presence of an appreciable recombination current. If the forward current is dominated by a recombination or diffusion current, the ideality factor with a smaller leakage current should be smaller than that with a larger leakage current. However, if the Schottky contact is formed locally in the junction region, the above phenomena can appear adversely. Fig. 7 shows that the forward current is dominated by diffusion current in the area-type diode and recombination current in the perimeter-type diode. Hence, it can be said that Schottky contact is not formed in the depletion region. Therefore, from the data of Fig. 4 to Fig. 7, it can be concluded that the primary field-enhanced carrier transport of the reverse junction current is the Poole-Frenkel barrier lowering due to the silicide-related traps. 2. Physical Analysis of Shallow Junction and N 2 PAI Effects Fig. 8 shows SIMS profiles of the n+ source/drain region (As/50 KeV + P/35 KeV), and the depth of the n+-p junction is about 0.13 µm. Fig. 9 shows a SCM image of a perimeter junction with STI. The dark fringes show the junction area and different material; hence, the n+-p junction depth can be extracted as about 0.14 µm from the silicon surface. This is relatively well consistent with the junction depth measured by SIMS, and the junction contour in Fig. 9 abnormally bends upward near the STI, showing the formation of the shallower junction at

5 Characterization and Improvement of Reverse Leakage Kyong-Jin Hwang et al. -S799- IV. CONCLUSIONS Fig. 11. TEM images of perimeter type diode with N 2 PAI: (a) before, and (b) after 30-sec thermal stress twice at 950 C. In this paper, the junction leakage mechanism of a shallow junction with Co-silicide in 90-nm CMOS technology is studied in depth. The main cause of the increase of junction leakage current is the Poole-Frenkel barrier lowering due to the Co-related traps near the junction. It is shown that there is no formation of a Schottky contact in the junction through the investigation of the reverse current for Schottky-barrier lowering and the ideality factor of the forward bias current. It is also shown that N 2 PAI was highly efficient in retarding cobalt diffusion during high-temperature post-silicidation processes. Hence, a decrease of junction leakage and an improvement of thermal stability of Co-silicide were obtained by N 2 PAI, especially for the perimeter-type diode. ACKNOWLEDGMENTS The authors would like to thank the engineers in Process Development, Magnachip, and members of the Mi- DAS Laboratory, Chungnam National University, for the help in device fabrication and extensive advice. Hi-Deok Lee also acknowledges support by the National Program for Tera-level Nano devices of the Ministry of Science and Technology as one of the 21 st Frontier Programs. Fig. 12. SIMS profile of cobalt in the n+ Source/Drain regions before and after thermal stress with and without N 2 PAI. that region. Therefore, the higher leakage current in the silicided junctions, in particular for the perimeter diode, can be attributed to the formation of the shallower junctions at the active edge due to the bending of the junction profile. To investigate the thermal stability of Co-silicide, thermal stress at 950 C RTA was applied twice after formation of the Co-silicide. Fig. 10 shows the agglomeration of the CoSi 2 after thermal treatment. However, CoSi 2 with the N 2 PAI scheme shows little change from its original shape, even after severe thermal stress, as shown in Fig. 11. A previous study [7] showed that nitrogen makes the grain of the Co-silicide smaller, so it prevents silicide from agglomerating [11]. However, we found that nitrogen hinders diffusion of cobalt in a high thermal process from the SIMS depth profile as in Fig. 12. After thermal stress, a small change of the cobalt profile is shown for the shallow junction with N 2 PAI, compared to that without N 2 PAI. It is noteworthy that the nitrogen concentration has a peak at the center of the high-concentration region of the cobalt. Therefore, N 2 PAI retards the diffusion of cobalt and hence suppresses silicide agglomeration. REFERENCES [1] A. Chatterjee, M. Rodder and I. C. Chen, IEEE Trans. Electron Devices, 45, 1246 (1998). [2] K. Goto, A. Fushida, J. Sukegawa, K. Kawamura, T. Yamazaki and T. Sugii, IEDM Tech. Dig. (Washington DC, Dec., 1995), p [3] H. S. Park, H. J. Jung and W. K. Choi, J. Korean Phys. Soc. 44, 1594 (2004). [4] J. H. Yang, J. H. Oh, W. J. Choi, S. J. Lee, K. W. Park and K. J. Im, J. Korean Phys. Soc. 44, 423 (2004). [5] Y. M. Choi, J. Y. Kim, M. Y. Jeong, H. J. Kim, H. S. Kim, S. E. Kim, B. J. Park, I. B. Chung, D. I. Kim, J. W. Lee, H. K. Hwang, Y. S. Hwang, D. S. Hwang, J. M. Park, M. H. Jo, D. H. Kim, N. J. Kang, Y. J. Park and Kinam Kim, J. Korean Phys. Soc. 44, 108 (2004). [6] S. Pramanick, Y. N. Erokhin and G. A. Rozgonyi, Appl. Phys. Lett. 63, 1933 (1993). [7] G. Wein-Town Sun, Ming-Chi Liaw and Charles Ching- Hsiang Hsu, IEEE Electron Device Lett. 19, (1998). [8] J. H. Lee, M. J. Jang, K.S Youn, Y. J. Park and H. G. Youn, J. Korean Phys. Soc. 40, 619 (2002). [9] H. D. Lee, IEEE Trans. Electron Dev. 47, 762 (2000). [10] M. J. Jang, J. H. Lee, Y. J. Park and H. K. Yoon, J. Korean Phys. Soc. 40, 619 (2002). [11] J. U. Bae, D. K. Shon and J. S. Park, VLSI Technology Digest of Technical papers 5A-3 (1999).