Bonding Technologies for 3D-Packaging

Transcription

1 Dresden University of Technology / Karsten Meier, Klaus-Juergen Wolter NanoZEIT SEMICON Europa 2011 Dresden

2 System integration by SoC or SiP solutions offer advantages regarding design efforts, performance, power efficiency, device size, package & process cost, [Eniac: European technology platform nanoelectronics, http//:nano.sdu.dk/pdf/nanoelectronics-sra(2).pdf, 2005, p. 31.] slide 2

3 Content Introduction 3D-integration technologies Bonding technologies for Package-on-Package Die-to-Wafer technologies Conclusions slide 3

4 Introduction: Status of System in Package [Roellig M., Beiträge zur Bestimmung von mechanischen Kennwerten an produktkonformen Lotkontakten der Elektronik, Dissertation, Technische Universität Dresden, 2008] slide 4

5 Introduction: Young Researchers Group Production Concepts Technology [Tummala, R., PRC Georgia Tech, USA] Research focusing on -concepts - technology -production of/for highly reliable 3D-Microsystems slide 5

6 Content Introduction 3D-integration technologies Bonding technologies for Package-on-Package Die-to-Wafer technologies Conclusions slide 6

7 Package-on-Package: Principles Stacked BGA-PoP with wire bonds or FC interconnects [Pahlke S., Beiträge zur Second-Level- Charakterisierung von 3D-Package-on Package, Diploma Thesis, Technische Universität Dresden, 2011] FC interconnect wire bonds Interposer-PoP [Das R. N. et al., ECTC, 2011] TMV-PoP [Smith L., Solid State Technology, Vol. 54, Issue 7, 2011] TSV-PoP [Cheah B. E. et al., ECTC, 2011] slide 7

8 Package-on-Package Pro s & Con s: + Compatible to common SMT processes + Integration of passive components + Chip design independent from package + Testability, cost effective, high reliability - Limited integration density compared to SiC solutions - Warpage of sub-packages Applications: Smart phones, tablet PCs, SSD drives, Memory (die stack) on top of logic/processor unit (single die) High density memory package (multiple die stack PoP) slide 8

9 Package-on-Package: Reliability of Solder Bonds PoP devices in e.g. smart phones face moderate thermal cycles but serious mechanical drops Solder joints still remain one of the major failure sites, especially at the bottom package Detailed knowledge on solder material behaviour (creep, high strain rate) leads to optimised reliability Selection of solder alloy essentially effects the PoP lifetime 63 %-lifetime of 14x14 mm² PoP under -40/+125 C 30 min dwell TCT and 12x12 mm² PoP under drop impact *up to 1750 TCT cycles no significant failure [Pahlke S., Beiträge zur Second-Level- Charakterisierung von 3D-Package-on Package, Diploma Thesis, Technische Universität Dresden, 2011] slide 9

10 Package-on-Package: Reliability of Solder Bonds The use of underfiller significantly enhances the PoP solder joint reliability Application to all PoP-levels to prevent a failure site shift Selection of underfiller has to match both thermo-cycling and drop loads as well as processing and cost needs Adhesion to the package is important 63 %-lifetime of 14x14 mm² PoP under -40/+125 C 30 min dwell TCT and 12x12 mm² PoP under drop impact without or with underfill *up to 1750 TCT cycles no significant failure [Pahlke S., Beiträge zur Second-Level- Charakterisierung von 3D-Package-on Package, Diploma Thesis, Technische Universität Dresden, 2011] slide 10

11 Package-on-Package: Future Developments PoP design - Integration of novel interconnect technologies: solder ball or Cu pillar (2 nd level) TSV (interposer or 1 st level) SLID (stacked dies) nanowire-filled adhesive film (ACANWF, bottom die) organic or silicon interposer compliancy high density, short high density, no re-melt very high density, TIM matching CTE stacked thin dies SLID interconnects ACANWF interconnect Si-interposer TSVs TMVs organic interposer solder balls slide 11

12 Content Introduction 3D-integration technologies Bonding technologies for Package-on-Package Die-to-Wafer technologies Conclusions slide 12

13 Die-to-Wafer: SLID Motivation & Concept Cu-Sn phase diagram SLID Cu-Sn Au-Sn Cu-SnAg thermostable joints (IMCs) enables multistacking of chips small joints (<10µm) low bond loads relatively simple processing low-lost technology 1. before bonding 2. bonding 3. complete transition to IMCs slide 13

14 Die-to-Wafer: SLID Research goals: Study diffusion kinetics Adjust cleaning process Optimisation of bonding conditions Reliability characterisation Backscattered SEM image of the Cu/Sn interconnect showing intermetallic phases (Cu 6 Sn 5,Cu 3 Sn) and voids slide 14

15 Die-to-Wafer: Self Alignment Principles Self-alignment for electronics packaging: Well-known phenomenon with SMT: self-alignment by liquid solder Reflow Various research on self-alignment in the past: by liquid: magnetic: electrostatic: surface tension Capillary action S.B. Shetye et al., University of Florida J. Dalin, J. Wilde Universität Freiburg Basic principle: force on the component to minimise free energy slide 15

16 Die-to-Wafer: z-self Alignment 3D die stacking assembly of warped thin dies: z-self alignment to reduce die warpage Use capillary action Influence of intitial warpage Wetting behaviour Geometry effects (pitch, gap height, volume of the liquid) Behaviour of the liquid (viscosity, curing demands) Temperature effects (intrinsic stresses) Enable integrated interconnect process warped die liquid substrate slide 16

17 Die-to-Wafer: z-self Alignment Orientation of the initial warpage (die size 10x10 mm², 50 µm; warpage 47 µm) die warpage [µm] initial state under capillary action Warpage reduction by >85% concave convex die warpage orientation: concave convex slide 17

18 Die-to-Wafer: Nanowire arrays for 3D bonding Film filled with vertically oriented nano-scaled interconnects: Ongoing demand for higher I/Os and smaller size Need for compliant interconnects Need for thermal management Template processing (thinning, create nano-sized pores) Pore filling Transition of nanowires into film (ACANWF) Chip level ACANWF TSV Passivation layer SiO 2 Adhesion promoter (SiO 2, TaN, ) Si TSV (Cu) Active die Cu bumps ACANWF Interposer slide 18

19 Die-to-Wafer: Nano Wire Arrays for 3D Bonding a)sem images of AAO template p = 100 nm, d = 50 nm b)scheme of the electrodeposition of NWs in AAO membranes c) SEM images of electrodeposited Ag NWs still inside the template l = 20 µm slide 19

20 Die-to-Wafer: TSV - dimensions TSV-layers Typical diameters: 5 20 µm Aspect ratio: up to 1:10 (ITRS predicts 20:1) Isolation (SiO 2 ) 400 nm Barrier-Layer (Ta/TaN) respectively 80 nm Seed-Layer (Cu) 600 nm Etched Si (Bosch process) [Lerner et al., FutureFab, Issue 26, 2008] Scallops in Si and SiO 2 - isolation layer unfilled TSVs (d=5µm) Cu-filled TSVs (d=20µm) [Wolf et al., ESTC, 2010] [Powel et al., IITC, 2008] slide 20 [Laviron et al., ECTC, 2009] [Wolf et al., ESTC, 2010]

21 Die-to-Wafer: TSV Cu grain structure Cu grain structure influences mechanical behaviour Strong anisotropy depending on crystal orientation Small size TSVs potentially contain only a few grain orientations Mechanical behaviour is essential for simulation work (FEM) Model performance restricts covering actual grain structure Analyse Cu grain structure depending on TSV size, processing and annealing conditions (EBSD) Model a characteristic section of one TSV Determine an effective material description EBSD mapping: [001] Inverse pole figure slide 21

22 Die-to-Wafer: TSV - FEM Cu grain structure influences mechanical behaviour 2D FEM model automatically build from a EBSD measurement (grain structure and orientation) Application of tensile loads Determine effective elastic behaviour Early result: Important for smaller TSVs (<10 µm) σ yy slide 22

23 Content Introduction 3D-integration technologies Bonding technologies for Package-on-Package Die-to-Wafer technologies Conclusions slide 23

24 Conclusions Two major SiP approaches within 3D integration: die stacks KGD, performance, high integration, PoP testability, cost effective, flexibility, medium integration, PoP technology: Package for mobile applications ongoing development & improvement Good TCT and drop reliability design for low warpage Potential D2W-technologies: SLID for die stacking w/o re-melting key factors planarity and cleaning z-self alignment by capillary action for warpage reduction ACANWF shows potential for high density interconnections TSV simulation studies demand detailed but efficient material models slide 24

25 Thank you!